A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Yasuhiro Konishi; Katsumi Dosaka; Takahiro Komatsu; Yoshinori Inoue; Masaki Kumanoya; Youichi Tobita; Hideki Genjyo; Masao Nagatomo; Tsutomu Yoshihara

doi:10.1109/4.62131

A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

Yasuhiro Konishi^*, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara

^*この研究の対応する著者

研究成果: Article › 査読

7 被引用数 (Scopus)

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The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4 × 32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.

本文言語	English
ページ（範囲）	1112-1117
ページ数	6
ジャーナル	IEEE Journal of Solid-State Circuits
巻	25
号	5
DOI	https://doi.org/10.1109/4.62131
出版ステータス	Published - 1990 10月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/4.62131

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AU - Kumanoya, Masaki

AU - Tobita, Youichi

AU - Genjyo, Hideki

AU - Nagatomo, Masao

AU - Yoshihara, Tsutomu

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AB - The authors describe a DRAM with a battery-backup (BBU) mode, which allows automatic data retention with extremely reduced power consumption. The circuit techniques for reducing the refresh current and the back-bias-generator current are shown. The dissipated current required for data retention of 44 μA is achieved under typical conditions. This DRAM was fabricated with quad-poly and double-metal CMOS process technology. The memory array is divided into 4 × 32 subarrays. The finely divided array architecture is suitable for the fast access time and the multibit test mode.

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A 38-ns 4-Mb DRAM with a battery-backup (BBU) mode

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