TY - GEN
T1 - A 40-nm 8T SRAM with selective source line control of read bitlines and address preset structure
AU - Yoshimoto, S.
AU - Miyano, S.
AU - Takamiya, M.
AU - Shinohara, H.
AU - Kawaguchi, H.
AU - Yoshimoto, M.
PY - 2013/11/7
Y1 - 2013/11/7
N2 - This paper presents a 40-nm 8T SRAM in which bitlines are partially discharged by a selective source line control (SSLC) for low-power operation. The proposed SSLC scheme reduces a read bitline voltage swing in an unselected column with a floating source line (SL) of dedicated read ports. The SL is controlled by an additional NMOS switch that is turned on in a selected column, but the switch is kept off in the remaining unselected columns. The proposed scheme is effective for power reduction in successive address readouts through a single column. Furthermore, this paper introduces an address preset structure. The preset address enables the SRAM to be read out with no access time penalty for preferred use of the SSLC scheme. We fabricated a 16-Kb 8T SRAM test chip in a 40-nm CMOS process and observed that the proposed SSLC scheme with the address preset structure saves 38.1% of the readout power on average.
AB - This paper presents a 40-nm 8T SRAM in which bitlines are partially discharged by a selective source line control (SSLC) for low-power operation. The proposed SSLC scheme reduces a read bitline voltage swing in an unselected column with a floating source line (SL) of dedicated read ports. The SL is controlled by an additional NMOS switch that is turned on in a selected column, but the switch is kept off in the remaining unselected columns. The proposed scheme is effective for power reduction in successive address readouts through a single column. Furthermore, this paper introduces an address preset structure. The preset address enables the SRAM to be read out with no access time penalty for preferred use of the SSLC scheme. We fabricated a 16-Kb 8T SRAM test chip in a 40-nm CMOS process and observed that the proposed SSLC scheme with the address preset structure saves 38.1% of the readout power on average.
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U2 - 10.1109/CICC.2013.6658537
DO - 10.1109/CICC.2013.6658537
M3 - Conference contribution
AN - SCOPUS:84892640745
SN - 9781467361460
T3 - Proceedings of the Custom Integrated Circuits Conference
BT - Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, CICC 2013
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 35th Annual Custom Integrated Circuits Conference - The Showcase for Circuit Design in the Heart of Silicon Valley, CICC 2013
Y2 - 22 September 2013 through 25 September 2013
ER -