@inproceedings{a912837879d14404b7e52cb478dd2aa7,
title = "A 45-nm single-port and dual-port SRAM family with robust read/write stabilizing circuitry under DVFS environment",
abstract = "We propose an enhanced design solution for embedded SRAM macros under dynamic voltage and frequency scaling (DVFS) environment. The improved wordline suppression technique using replica cell transistors and passive resistances compensates the read stability against process variation, facilitating the Fab. portability. The negative bitline technique expands the write margin for not only 6T single-port (SP) cell but also 8T dual-port (DP) cell even at the 0.7 V lower supply voltage. Using 45-nm CMOS technology, we fabricated both SP and DP SRAMs with the proposed circuitry. We achieve robust operations from 0.7 V to 1.3 V wide supply voltage.",
keywords = "45nm, 6T, 8T, CMOS, DVFS, SRAM, Stability",
author = "K. Nii and M. Yabuuchi and Y. Tsukamoto and S. Ohbayashi and Y. Oda and K. Usui and T. Kawamura and N. Tsuboi and T. Iwasaki and K. Hashimoto and H. Makino and H. Shinohara",
year = "2008",
doi = "10.1109/VLSIC.2008.4586011",
language = "English",
isbn = "9781424418053",
series = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "212--213",
booktitle = "2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC",
note = "2008 Symposium on VLSI Circuits Digest of Technical Papers, VLSIC ; Conference date: 18-06-2008 Through 20-06-2008",
}