TY - GEN
T1 - A 45nm 2port 8T-SRAM using hierarchical replica bitline technique with immunity from simultaneous RAV access issues
AU - Ishikura, S.
AU - Kurumada, M.
AU - Terano, T.
AU - Yamagami, Y.
AU - Kotani, N.
AU - Satomi, K.
AU - Nii, K.
AU - Yabuuchi, M.
AU - Tsukamoto, Y.
AU - Ohbayashi, S.
AU - Oashi, T.
AU - Makino, H.
AU - Shinohara, H.
AU - Akamatsu, H.
PY - 2007
Y1 - 2007
N2 - We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BI-×512WL 64Kb 2P-SRAM macro which cell size is 0.597μm2 using these schemes was fabricated by 45nm LSTP CMOS process [1].
AB - We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with Shared local Amplifier (DBSA) realizes fast access time without increasing area penalty. We also show an additional important issue of a simultaneous Read and Write (R/W) access at the same row by using DBSA with the 8T-SBL memory cell. A rise of the storage node voltage causes the misreading. The Read End detecting Replica circuit (RER) and the Local read bit line with Dummy Capacitance (LDC) are introduced to solve this issue. A 128BI-×512WL 64Kb 2P-SRAM macro which cell size is 0.597μm2 using these schemes was fabricated by 45nm LSTP CMOS process [1].
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U2 - 10.1109/VLSIC.2007.4342740
DO - 10.1109/VLSIC.2007.4342740
M3 - Conference contribution
AN - SCOPUS:39749119399
SN - 9784900784048
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 254
EP - 255
BT - 2007 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
T2 - 2007 Symposium on VLSI Circuits, VLSIC
Y2 - 14 June 2007 through 16 June 2007
ER -