A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

Dajiang Zhou; Jinjia Zhou; Xun He; Ji Kong; Jiayi Zhu; Peilin Liu; Satoshi Goto

doi:10.1109/VLSIC.2010.5560311

A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

Dajiang Zhou^*, Jinjia Zhou, Xun He, Ji Kong, Jiayi Zhu, Peilin Liu, Satoshi Goto

^*この研究の対応する著者

研究成果: Conference contribution

16 被引用数 (Scopus)

抄録

An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which is at least 4.3× higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth is reduced which results in 58% DRAM power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving of 54%.

本文言語	English
ホスト出版物のタイトル	IEEE Symposium on VLSI Circuits, Digest of Technical Papers
ページ	171-172
ページ数	2
DOI	https://doi.org/10.1109/VLSIC.2010.5560311
出版ステータス	Published - 2010
外部発表	はい
イベント	2010 24th Symposium on VLSI Circuits, VLSIC 2010 - Honolulu, HI 継続期間: 2010 6月 16 → 2010 6月 18

Other

Other	2010 24th Symposium on VLSI Circuits, VLSIC 2010
City	Honolulu, HI
Period	10/6/16 → 10/6/18

ASJC Scopus subject areas

電子工学および電気工学
電子材料、光学材料、および磁性材料

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10.1109/VLSIC.2010.5560311

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@inproceedings{3df32e6f3dec4e8193a0dc946087aa52,

title = "A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip",

abstract = "An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which is at least 4.3× higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth is reduced which results in 58% DRAM power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving of 54%.",

author = "Dajiang Zhou and Jinjia Zhou and Xun He and Ji Kong and Jiayi Zhu and Peilin Liu and Satoshi Goto",

year = "2010",

doi = "10.1109/VLSIC.2010.5560311",

language = "English",

isbn = "9781424476367",

pages = "171--172",

booktitle = "IEEE Symposium on VLSI Circuits, Digest of Technical Papers",

note = "2010 24th Symposium on VLSI Circuits, VLSIC 2010 ; Conference date: 16-06-2010 Through 18-06-2010",

}

TY - GEN

T1 - A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

AU - Zhou, Dajiang

AU - Zhou, Jinjia

AU - He, Xun

AU - Kong, Ji

AU - Zhu, Jiayi

AU - Liu, Peilin

AU - Goto, Satoshi

PY - 2010

Y1 - 2010

N2 - An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which is at least 4.3× higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth is reduced which results in 58% DRAM power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving of 54%.

AB - An H.264/AVC HP video decoder is implemented in 90nm CMOS. Its maximum throughput reaches 4096×2160@60fps, which is at least 4.3× higher than the state-of-the-art. By using partial MB reordering and lossless frame recompression, 51% of DRAM bandwidth is reduced which results in 58% DRAM power saving. Meanwhile, various efficient parallelization techniques contribute to a core energy saving of 54%.

UR - http://www.scopus.com/inward/record.url?scp=77958004818&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77958004818&partnerID=8YFLogxK

U2 - 10.1109/VLSIC.2010.5560311

DO - 10.1109/VLSIC.2010.5560311

M3 - Conference contribution

AN - SCOPUS:77958004818

SN - 9781424476367

SP - 171

EP - 172

BT - IEEE Symposium on VLSI Circuits, Digest of Technical Papers

T2 - 2010 24th Symposium on VLSI Circuits, VLSIC 2010

Y2 - 16 June 2010 through 18 June 2010

ER -

A 530Mpixels/s 4096×2160@60fps H.264/AVC high profile video decoder chip

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