A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

Takeshi Nakayama; Shin ichi Kobayashi; Yoshikazu Miyawaki; Yasushi Terada; Natsuo Ajika; Makoto Ohi; Hideaki Arima; Takayuki Matsukawa; Tsutomu Yoshihara; Kimio Suzuki

doi:10.1109/4.98978

A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

Takeshi Nakayama^*, Shin ichi Kobayashi, Yoshikazu Miyawaki, Yasushi Terada, Natsuo Ajika, Makoto Ohi, Hideaki Arima, Takayuki Matsukawa, Tsutomu Yoshihara, Kimio Suzuki

^*この研究の対応する著者

研究成果: Article › 査読

2 被引用数 (Scopus)

抄録

An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks. in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm × 2.0 μm and a chip size of 6.5 mm × 18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process.

本文言語	English
ページ（範囲）	1600-1605
ページ数	6
ジャーナル	IEEE Journal of Solid-State Circuits
巻	26
号	11
DOI	https://doi.org/10.1109/4.98978
出版ステータス	Published - 1991 11月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/4.98978

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abstract = "An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks. in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm × 2.0 μm and a chip size of 6.5 mm × 18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process.",

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AU - Nakayama, Takeshi

AU - Kobayashi, Shin ichi

AU - Miyawaki, Yoshikazu

AU - Terada, Yasushi

AU - Ajika, Natsuo

AU - Ohi, Makoto

AU - Arima, Hideaki

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

AU - Suzuki, Kimio

PY - 1991/11

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AB - An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks. in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm × 2.0 μm and a chip size of 6.5 mm × 18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process.

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A 60-ns 16-Mb flash EEPROM with program and erase sequence controller

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