An erase and program control system has been implemented in a 60-ns 16-Mb flash EEPROM. The memory array is divided into 64 blocks. in each block, erase pulse application and erase-verify operation are employed individually. The erase and program sequence is controlled by an internal sequence controller composed of a synchronous circuit with an on-chip oscillator. A 60-ns access time has been achieved with a differential sensing scheme utilizing dummy cells. A cell size of 1.8 μm × 2.0 μm and a chip size of 6.5 mm × 18.4 mm were achieved using a simple stacked gate cell structure and 0.6-μm CMOS process.
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