A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Shigeki Ohbayashi; Makoto Yabuuchi; Koji Nil; Yasumasa Tsukamoto; Susumu Imaoka; Yuji Oda; Tsutomu Yoshihara; Motoshige Igarashi; Masahiko Takeuchi; Hiroshi Kawashima; Yasuo Yamaguchi; Kazuhiro Tsukamoto; Masahide Inuishi; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara

doi:10.1109/JSSC.2007.891648

A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

Shigeki Ohbayashi^*, Makoto Yabuuchi, Koji Nil, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

^*この研究の対応する著者

研究成果: Article › 査読

109 被引用数 (Scopus)

抄録

In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm² SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

本文言語	English
ページ（範囲）	820-829
ページ数	10
ジャーナル	IEEE Journal of Solid-State Circuits
巻	42
号	4
DOI	https://doi.org/10.1109/JSSC.2007.891648
出版ステータス	Published - 2007 4月
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/JSSC.2007.891648

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Ohbayashi, S., Yabuuchi, M., Nil, K., Tsukamoto, Y., Imaoka, S., Oda, Y., Yoshihara, T., Igarashi, M., Takeuchi, M., Kawashima, H., Yamaguchi, Y., Tsukamoto, K., Inuishi, M., Makino, H., Ishibashi, K., & Shinohara, H. (2007). A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits. IEEE Journal of Solid-State Circuits, 42(4), 820-829. https://doi.org/10.1109/JSSC.2007.891648

Ohbayashi, S, Yabuuchi, M, Nil, K, Tsukamoto, Y, Imaoka, S, Oda, Y, Yoshihara, T, Igarashi, M, Takeuchi, M, Kawashima, H, Yamaguchi, Y, Tsukamoto, K, Inuishi, M, Makino, H, Ishibashi, K & Shinohara, H 2007, 'A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits', IEEE Journal of Solid-State Circuits, vol. 42, no. 4, pp. 820-829. https://doi.org/10.1109/JSSC.2007.891648

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abstract = "In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm2 SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.",

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AU - Ohbayashi, Shigeki

AU - Yabuuchi, Makoto

AU - Nil, Koji

AU - Tsukamoto, Yasumasa

AU - Imaoka, Susumu

AU - Oda, Yuji

AU - Yoshihara, Tsutomu

AU - Igarashi, Motoshige

AU - Takeuchi, Masahiko

AU - Kawashima, Hiroshi

AU - Yamaguchi, Yasuo

AU - Tsukamoto, Kazuhiro

AU - Inuishi, Masahide

AU - Makino, Hiroshi

AU - Ishibashi, Koichiro

AU - Shinohara, Hirofumi

PY - 2007/4

Y1 - 2007/4

N2 - In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm2 SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

AB - In the sub-100-nm CMOS generation, a large local Vth variability degrades the 6T-SRAM cell stability, so that we have to consider this local variability as well as the global variability to achieve high-yield SRAM products. Therefore, we need to employ some assist circuits to expand the SRAM operating margin. We propose a variability-tolerant 6T-SRAM cell layout and new circuit techniques to improve both the read and the write operating margins in the presence of a large Vth variability. By applying these circuit techniques to a 0.494-μm2 SRAM cell with a β ratio of 1, which is an extremely small cell size, we can achieve a high-yield 8M-SRAM for a wide range of Vth values using a 65-nm low stand-by power (LSTP) CMOS technology.

KW - 65-nm CMOS

KW - 6T-SRAM

KW - Assist circuit

KW - CMOS

KW - Embedded SRAM

KW - SRAM

KW - Vth curve

KW - Vth-variability

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A 65-nm SoC embedded 6T-SRAM designed for manufacturability with read and write operation stabilizing circuits

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