A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

Shigeki Ohbayashi; Makoto Yabuuchi; Kazushi Kono; Yuji Oda; Susumu Imaoka; Keiichi Usui; Toshiaki Yonezu; Takeshi Iwamoto; Koji Nii; Yasumasa Tsukamoto; Masashi Arakawa; Takahiro Uchida; Masakazu Qkada; Atsushi Ishii; Hiroshi Makino; Koichiro Ishibashi; Hirofumi Shinohara

doi:10.1109/ISSCC.2007.373507

A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

Shigeki Ohbayashi^*, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Qkada, Atsushi Ishii, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

^*この研究の対応する著者

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

本文言語	English
ホスト出版物のタイトル	2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	488-490
ページ数	3
ISBN（印刷版）	1424408539, 9781424408535
DOI	https://doi.org/10.1109/ISSCC.2007.373507
出版ステータス	Published - 2007
外部発表	はい
イベント	54th IEEE International Solid-State Circuits Conference, ISSCC 2007 - San Francisco, CA, United States 継続期間: 2007 2月 11 → 2007 2月 15

出版物シリーズ

名前	Digest of Technical Papers - IEEE International Solid-State Circuits Conference
ISSN（印刷版）	0193-6530

Other

Other	54th IEEE International Solid-State Circuits Conference, ISSCC 2007
国/地域	United States
City	San Francisco, CA
Period	07/2/11 → 07/2/15

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

文献へのアクセス

10.1109/ISSCC.2007.373507

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引用スタイル

Ohbayashi, S., Yabuuchi, M., Kono, K., Oda, Y., Imaoka, S., Usui, K., Yonezu, T., Iwamoto, T., Nii, K., Tsukamoto, Y., Arakawa, M., Uchida, T., Qkada, M., Ishii, A., Makino, H., Ishibashi, K., & Shinohara, H. (2007). A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers (pp. 488-490). Article 4242478 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISSCC.2007.373507

A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. / Ohbayashi, Shigeki; Yabuuchi, Makoto; Kono, Kazushi その他.
2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. p. 488-490 4242478 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

研究成果: Conference contribution

Ohbayashi, S, Yabuuchi, M, Kono, K, Oda, Y, Imaoka, S, Usui, K, Yonezu, T, Iwamoto, T, Nii, K, Tsukamoto, Y, Arakawa, M, Uchida, T, Qkada, M, Ishii, A, Makino, H, Ishibashi, K & Shinohara, H 2007, A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. in 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers., 4242478, Digest of Technical Papers - IEEE International Solid-State Circuits Conference, Institute of Electrical and Electronics Engineers Inc., pp. 488-490, 54th IEEE International Solid-State Circuits Conference, ISSCC 2007, San Francisco, CA, United States, 07/2/11. https://doi.org/10.1109/ISSCC.2007.373507

Ohbayashi S, Yabuuchi M, Kono K, Oda Y, Imaoka S, Usui K その他. A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. In 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc. 2007. p. 488-490. 4242478. (Digest of Technical Papers - IEEE International Solid-State Circuits Conference). doi: 10.1109/ISSCC.2007.373507

Ohbayashi, Shigeki ; Yabuuchi, Makoto ; Kono, Kazushi その他. / A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die. 2007 IEEE International Solid-State Circuits Conference, ISSCC - Digest of Technical Papers. Institute of Electrical and Electronics Engineers Inc., 2007. pp. 488-490 (Digest of Technical Papers - IEEE International Solid-State Circuits Conference).

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abstract = "A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.",

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AU - Imaoka, Susumu

AU - Usui, Keiichi

AU - Yonezu, Toshiaki

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AU - Arakawa, Masashi

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AB - A wafer-level burn-in (WLBI) mode, a leak-bit redundancy and a small, highly reliable electrically trimmable (e-trim) fuse repair scheme for an embedded 6T-SRAM is used to achieve a known-good-die SoC. A 16Mb SRAM is fabricated with these techniques using a 65nm low-standby-power technology, and its operation is verified. The WLBI mode has a speed penalty of 50ps. The leak-bit redundancy area penalty is less than 2%.

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A 65nm embedded SRAM with wafer-level burn-in mode, leak-bit redundancy and E-trim fuse for known good die

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出版物シリーズ

Other

ASJC Scopus subject areas

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