A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

Zhixiang Chen; Xiao Peng; Xiongxin Zhao; Leona Okamura; Dajiang Zhou; Satoshi Goto

doi:10.1109/ASPDAC.2013.6509569

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

Zhixiang Chen, Xiao Peng, Xiongxin Zhao, Leona Okamura, Dajiang Zhou, Satoshi Goto

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.

本文言語	English
ホスト出版物のタイトル	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
ページ	87-88
ページ数	2
DOI	https://doi.org/10.1109/ASPDAC.2013.6509569
出版ステータス	Published - 2013
イベント	2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 - Yokohama 継続期間: 2013 1月 22 → 2013 1月 25

Other

Other	2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013
City	Yokohama
Period	13/1/22 → 13/1/25

ASJC Scopus subject areas

電子工学および電気工学
コンピュータサイエンスの応用
コンピュータグラフィックスおよびコンピュータ支援設計

UN SDG

この成果は、次の持続可能な開発目標に貢献しています

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10.1109/ASPDAC.2013.6509569

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引用スタイル

Chen, Z, Peng, X, Zhao, X, Okamura, L, Zhou, D & Goto, S 2013, A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS. in Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC., 6509569, pp. 87-88, 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013, Yokohama, 13/1/22. https://doi.org/10.1109/ASPDAC.2013.6509569

@inproceedings{2f7fbebd22cd48deb9919d01df5c5099,

title = "A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS",

abstract = "An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.",

author = "Zhixiang Chen and Xiao Peng and Xiongxin Zhao and Leona Okamura and Dajiang Zhou and Satoshi Goto",

year = "2013",

doi = "10.1109/ASPDAC.2013.6509569",

language = "English",

isbn = "9781467330299",

pages = "87--88",

booktitle = "Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC",

note = "2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013 ; Conference date: 22-01-2013 Through 25-01-2013",

}

TY - GEN

T1 - A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

AU - Chen, Zhixiang

AU - Peng, Xiao

AU - Zhao, Xiongxin

AU - Okamura, Leona

AU - Zhou, Dajiang

AU - Goto, Satoshi

PY - 2013

Y1 - 2013

N2 - An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.

AB - An LDPC decoder in 65nm CMOS targeting WPAN (IEEE 802.15.3c) is presented with measurement results. A modified-PCM based message permutation strategy with compatible data flow is proposed to solve the network problem raised by high parallelism LDPC decoding. Compared to the state-of-art, decoder chip achieves 17.7%, 33.5% and 49% improvements in chip density, gate count and energy efficiency, respectively.

UR - http://www.scopus.com/inward/record.url?scp=84877725155&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84877725155&partnerID=8YFLogxK

U2 - 10.1109/ASPDAC.2013.6509569

DO - 10.1109/ASPDAC.2013.6509569

M3 - Conference contribution

AN - SCOPUS:84877725155

SN - 9781467330299

SP - 87

EP - 88

BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

T2 - 2013 18th Asia and South Pacific Design Automation Conference, ASP-DAC 2013

Y2 - 22 January 2013 through 25 January 2013

ER -

A 6.72-Gb/s, 8pJ/bit/iteration WPAN LDPC decoder in 65nm CMOS

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Other

ASJC Scopus subject areas

UN SDG

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