A 7-round parallel hardware-saving accelerator for Gaussian and DoG pyramid construction part of SIFT

Jingbang Qiu*, Tianci Huang, Takeshi Ikenaga

*この研究の対応する著者

研究成果: Conference contribution

6 被引用数 (Scopus)

抄録

SIFT, short for Scale Invariant Feature Transform, is regarded as one of the most robust feature detection algorithms. The Gaussian and DoG Pyramid Construction part, functioning as computation basis and searching spaces for other parts, proves fatal to the system. In this paper, we present an FPGA-implementable hardware accelerator for this part. Stratified Gaussian Convolution scheme and 7-Round Parallel Computation scheme are introduced to reduce the hardware cost and improve process speed, meanwhile keeping high accuracy. In our experiment, our proposal successfully realizes a system with max clock frequency of 95.0 MHz, and on-system process speed of up to 21 fps for VGA format images. Hardware cost of Slice LUTs is reduced by 12.1% compared with traditional work. Accuracy is kept as high as 98.27% against original software solution. Our proposed structure proves to be suitable for real-time SIFT systems.

本文言語English
ホスト出版物のタイトルComputer Vision, ACCV 2009 - 9th Asian Conference on Computer Vision, Revised Selected Papers
ページ75-84
ページ数10
PART 3
DOI
出版ステータスPublished - 2010 12月 29
イベント9th Asian Conference on Computer Vision, ACCV 2009 - Xi'an, China
継続期間: 2009 9月 232009 9月 27

出版物シリーズ

名前Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
番号PART 3
5996 LNCS
ISSN(印刷版)0302-9743
ISSN(電子版)1611-3349

Conference

Conference9th Asian Conference on Computer Vision, ACCV 2009
国/地域China
CityXi'an
Period09/9/2309/9/27

ASJC Scopus subject areas

  • 理論的コンピュータサイエンス
  • コンピュータ サイエンス(全般)

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