This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.
|ホスト出版物のタイトル||Proceedings of the International Symposium on Low Power Electronics and Design|
|出版ステータス||Published - 2011|
|イベント||17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka|
継続期間: 2011 8月 1 → 2011 8月 3
|Other||17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011|
|Period||11/8/1 → 11/8/3|
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