A 98 GMACs/W 32-core vector processor in 65nm CMOS

Xun He; Dajiang Zhou; Xin Jin; Satoshi Goto

doi:10.1109/ISLPED.2011.5993669

A 98 GMACs/W 32-core vector processor in 65nm CMOS

Xun He^*, Dajiang Zhou, Xin Jin, Satoshi Goto

^*この研究の対応する著者

研究成果: Conference contribution

抄録

This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.

本文言語	English
ホスト出版物のタイトル	Proceedings of the International Symposium on Low Power Electronics and Design
ページ	373-378
ページ数	6
DOI	https://doi.org/10.1109/ISLPED.2011.5993669
出版ステータス	Published - 2011
イベント	17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011 - Fukuoka 継続期間: 2011 8月 1 → 2011 8月 3

Other

Other	17th IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2011
City	Fukuoka
Period	11/8/1 → 11/8/3

ASJC Scopus subject areas

工学（全般）

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10.1109/ISLPED.2011.5993669

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title = "A 98 GMACs/W 32-core vector processor in 65nm CMOS",

abstract = "This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.",

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author = "Xun He and Dajiang Zhou and Xin Jin and Satoshi Goto",

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language = "English",

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AU - Jin, Xin

AU - Goto, Satoshi

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N2 - This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.

AB - This paper presents a high-performance dual-issue 32-core SIMD platform for image and video processing. Eight cores with a 4-ports L2 cache are connected by CIB bus as a cluster. Four clusters are connected by mesh network. The proposed hierarchical network can provide 192 GB/sintercore communication BW in average. To reduce coherence operation in large-scale SMP, an application specified protocol is proposed. Comparing with MOESI, 67.8% of L1 Cache energy can be saved in 32 cores case. It can achieve a peak performance of 375 GMACs and 98 GMACs/W in 65 nm CMOS.

KW - Cache coherence

KW - Multicore Processor

KW - NoC

KW - SIMD

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BT - Proceedings of the International Symposium on Low Power Electronics and Design

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A 98 GMACs/W 32-core vector processor in 65nm CMOS

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