A bitwidth-aware high-level synthesis algorithm using operation chainings for tiled-DR architectures

Mathematics

• High-level Synthesis 100%
• Architecture 56%
• Controller 48%
• Hardware Design 21%
• Hardware Implementation 19%
• Unit 17%
• Latency 16%
• High Performance 16%
• Interconnection 14%
• Optimise 13%
• Experimental Results 12%
• Term 6%

Engineering & Materials Science

• High level synthesis 64%
• Controllers 27%
• Tile 14%
• Computer hardware 7%
• Networks (circuits) 6%