A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

Hiroshi Fuketa; Satoshi Iida; Tadashi Yasufuku; Makoto Takamiya; Masahiro Nomura; Hirofumi Shinohara; Takayasu Sakurai

doi:10.1145/2024724.2024942

A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates

Hiroshi Fuketa^*, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

^*この研究の対応する著者

研究成果: Conference contribution

21 被引用数 (Scopus)

抄録

In this paper, a closed-form expression for estimating a minimum operating voltage (V_DDmin) of CMOS logic gates is proposed. V_DDmin is defined as the minimum supply voltage at which circuits can operate correctly. V_DDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that V_DDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

本文言語	English
ホスト出版物のタイトル	2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	984-989
ページ数	6
ISBN（印刷版）	9781450306362
DOI	https://doi.org/10.1145/2024724.2024942
出版ステータス	Published - 2011
外部発表	はい

出版物シリーズ

名前	Proceedings - Design Automation Conference
ISSN（印刷版）	0738-100X

ASJC Scopus subject areas

コンピュータサイエンスの応用
制御およびシステム工学
電子工学および電気工学
モデリングとシミュレーション

文献へのアクセス

10.1145/2024724.2024942

他のファイルとリンク

引用スタイル

Fuketa, H., Iida, S., Yasufuku, T., Takamiya, M., Nomura, M., Shinohara, H., & Sakurai, T. (2011). A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates. In 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011 (pp. 984-989). 記事 5981890 (Proceedings - Design Automation Conference). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/2024724.2024942

A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates. / Fuketa, Hiroshi; Iida, Satoshi; Yasufuku, Tadashi その他.
2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. Institute of Electrical and Electronics Engineers Inc., 2011. p. 984-989 5981890 (Proceedings - Design Automation Conference).

研究成果: Conference contribution

Fuketa, H, Iida, S, Yasufuku, T, Takamiya, M, Nomura, M, Shinohara, H & Sakurai, T 2011, A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates. in 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011., 5981890, Proceedings - Design Automation Conference, Institute of Electrical and Electronics Engineers Inc., pp. 984-989. https://doi.org/10.1145/2024724.2024942

Fuketa H, Iida S, Yasufuku T, Takamiya M, Nomura M, Shinohara H その他. A closed-form expression for estimating minimum operating voltage (V _DDmin) of CMOS logic gates. In 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011. Institute of Electrical and Electronics Engineers Inc. 2011. p. 984-989. 5981890. (Proceedings - Design Automation Conference). doi: 10.1145/2024724.2024942

@inproceedings{f41212e4a0284f758afaaa21dcaeaf2f,

title = "A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates",

abstract = "In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process",

keywords = "Minimum operating voltage, subthreshold circuits, variations",

author = "Hiroshi Fuketa and Satoshi Iida and Tadashi Yasufuku and Makoto Takamiya and Masahiro Nomura and Hirofumi Shinohara and Takayasu Sakurai",

year = "2011",

doi = "10.1145/2024724.2024942",

language = "English",

isbn = "9781450306362",

series = "Proceedings - Design Automation Conference",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

pages = "984--989",

booktitle = "2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011",

}

TY - GEN

T1 - A closed-form expression for estimating minimum operating voltage (V DDmin) of CMOS logic gates

AU - Fuketa, Hiroshi

AU - Iida, Satoshi

AU - Yasufuku, Tadashi

AU - Takamiya, Makoto

AU - Nomura, Masahiro

AU - Shinohara, Hirofumi

AU - Sakurai, Takayasu

PY - 2011

Y1 - 2011

N2 - In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

AB - In this paper, a closed-form expression for estimating a minimum operating voltage (VDDmin) of CMOS logic gates is proposed. VDDmin is defined as the minimum supply voltage at which circuits can operate correctly. VDDmin of combinational circuits can be written as a linear function of the square-root of logarithm of the number of logic gates and its slope is proportional to the standard deviation of the within-die variation in the threshold voltage difference between PMOS and NMOS transistors. The proposed expression is verified with Monte Carlo simulations using various gate chains. The verification reveals that VDDmin of inverter chains can be estimated within 11% error. The expression is also verified with silicon measurements in a 65nm CMOS process

KW - Minimum operating voltage

KW - subthreshold circuits

KW - variations

UR - http://www.scopus.com/inward/record.url?scp=80052658521&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=80052658521&partnerID=8YFLogxK

U2 - 10.1145/2024724.2024942

DO - 10.1145/2024724.2024942

M3 - Conference contribution

AN - SCOPUS:80052658521

SN - 9781450306362

T3 - Proceedings - Design Automation Conference

SP - 984

EP - 989

BT - 2011 48th ACM/EDAC/IEEE Design Automation Conference, DAC 2011

PB - Institute of Electrical and Electronics Engineers Inc.

ER -