TY - JOUR
T1 - A cost-efficient high-performance dynamic TCAM with pipelined hierarchical searching and shift redundancy architecture
AU - Noda, Hideyuki
AU - Inoue, Kazunari
AU - Kuroiwa, Masayuki
AU - Igaue, Futoshi
AU - Yamamoto, Kouji
AU - Mattausch, Hans Jürgen
AU - Koide, Tetsushi
AU - Amo, Atsushi
AU - Hachisuka, Atsushi
AU - Soeda, Shinya
AU - Hayashi, Isamu
AU - Morishita, Fukashi
AU - Dosaka, Katsumi
AU - Arimoto, Kazutami
AU - Fujishima, Kazuyasu
AU - Anami, Kenji
AU - Yoshihara, Tsutomu
PY - 2005/1
Y1 - 2005/1
N2 - This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 μm 2. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm2 for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.
AB - This paper describes a 4.5-Mb dynamic ternary CAM (DTCAM) which is suitable for networking applications. A dynamic TCAM cell structure in 130-nm embedded DRAM technology is used to realize the small cell size of 3.59 μm 2. In addition, a novel array architecture of TCAM, the pipelined hierarchical searching (PHS) architecture, is proposed. The PHS architecture is found to be suitable for realizing small area penalty, high-throughput searching and low-voltage operation simultaneously. With the combination of the DTCAM cell and the PHS architecture, small silicon area of 32 mm2 for a fabricated 4.5-Mb DTCAM chip, high performance of 143 M searches per second and low power dissipation of 1.1 W have been achieved. To improve the yield of TCAMs, a novel shift redundancy technique is applied and estimated to result in 3.6-times yield improvement. These techniques and architectures described in this report are attractive for realizing cost-efficient, large-scale, high-performance TCAM chips.
KW - CMOS memory integrated circuits
KW - Embedded DRAM
KW - Network
KW - Ternary CAM
UR - http://www.scopus.com/inward/record.url?scp=19944425993&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=19944425993&partnerID=8YFLogxK
U2 - 10.1109/JSSC.2004.838016
DO - 10.1109/JSSC.2004.838016
M3 - Article
AN - SCOPUS:19944425993
SN - 0018-9200
VL - 40
SP - 245
EP - 251
JO - IEEE Journal of Solid-State Circuits
JF - IEEE Journal of Solid-State Circuits
IS - 1
ER -