TY - GEN
T1 - A DC-50 GHz, low insertion loss and high P1dB SPDT switch IC in 40-nm SOI CMOS
AU - Chen, Cuilin
AU - Xu, Xiao
AU - Yoshimasu, Toshihiko
N1 - Publisher Copyright:
© 2017 IEEE.
PY - 2017/6/28
Y1 - 2017/6/28
N2 - A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.
AB - A DC-50 GHz Single-Pole Double-Throw (SPDT) switch IC is designed, fabricated and fully evaluated on wafer in 40-nm SOI CMOS. The insertion loss of the SPDT switch IC is 0.99 dB at 20 GHz and 1.68 dB at 40 GHz, respectively. From 100 MHz to 50 GHz, the measured isolation is better than 15.8 dB. The input-referred 1-dB compression point (P1dB) is over 20 dBm at 10 GHz.
KW - SOI
KW - SPDT switch IC
KW - broadband
KW - high P1dB
KW - low insertion loss
UR - http://www.scopus.com/inward/record.url?scp=85044750434&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85044750434&partnerID=8YFLogxK
U2 - 10.1109/APMC.2017.8251363
DO - 10.1109/APMC.2017.8251363
M3 - Conference contribution
AN - SCOPUS:85044750434
T3 - Asia-Pacific Microwave Conference Proceedings, APMC
SP - 5
EP - 8
BT - 2017 Asia Pacific Microwave Conference, APMC 2017 - Proceedings
A2 - Pasya, Idnin
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2017 IEEE Asia Pacific Microwave Conference, APMC 2017
Y2 - 13 November 2017 through 16 November 2017
ER -