抄録
This paper proposes a fast depth-constrained technology mapping algorithm for logic-blocks composed of tree-structured lookup tables. First, we propose a technology mapping algorithm which minimizes the number of logic-blocks if an input Boolean network is a tree. Second, we propose a technology mapping algorithm which minimizes logic depth for any input Boolean network. Finally, we combine those two technology mapping algorithms and propose an algorithm which realizes technology mapping whose depth is bounded by a given upper bound dc. Experimental results demonstrate the effectiveness and efficiency of the proposed algorithm.
| 本文言語 | English |
|---|---|
| ページ（範囲） | 473-481 |
| ページ数 | 9 |
| ジャーナル | IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences |
| 巻 | E82-A |
| 号 | 3 |
| 出版ステータス | Published - 1999 1月 1 |
ASJC Scopus subject areas
- 信号処理
- コンピュータ グラフィックスおよびコンピュータ支援設計
- 電子工学および電気工学
- 応用数学