TY - JOUR
T1 - A fastweighted adder by reducing partial product for reconstruction in super-resolution
AU - Yoshihara, Hiromine
AU - Yanagisawa, Masao
AU - Togawa, Nozomu
PY - 2012
Y1 - 2012
N2 - In recent years, it is quite necessary to convert conventional low-resolution images to high-resolution ones at low cost. Super-resolution is a technique to remove the noise of observed images and restore its high frequencies. We focus on reconstruction-based super-resolution. Reconstruction requires large computation cost since it requires many images. In this paper, we propose a fast weighted adder for reconstruction-based super-resolution. From the viewpoint of reducing partial products, we propose two approaches to speed up a weighted adder. First, we use selector logics to halve its partial products. Second, we propose a weights-range limit method utilizing negative term. By applying our proposed approaches to a weighted adder, we can reduce carry propagations and our weighted adder can be designed by a fast circuit as compared to conventional ones. Experimental evaluations demonstrate that our weighted adder reduces its delay time by a maximum of 25.29% and its area to a maximum of 1/3, compared to conventional implementations.
AB - In recent years, it is quite necessary to convert conventional low-resolution images to high-resolution ones at low cost. Super-resolution is a technique to remove the noise of observed images and restore its high frequencies. We focus on reconstruction-based super-resolution. Reconstruction requires large computation cost since it requires many images. In this paper, we propose a fast weighted adder for reconstruction-based super-resolution. From the viewpoint of reducing partial products, we propose two approaches to speed up a weighted adder. First, we use selector logics to halve its partial products. Second, we propose a weights-range limit method utilizing negative term. By applying our proposed approaches to a weighted adder, we can reduce carry propagations and our weighted adder can be designed by a fast circuit as compared to conventional ones. Experimental evaluations demonstrate that our weighted adder reduces its delay time by a maximum of 25.29% and its area to a maximum of 1/3, compared to conventional implementations.
KW - Reconstruction
KW - Selector-logics
KW - Super-resolution
KW - Weighted adder
UR - http://www.scopus.com/inward/record.url?scp=84864945815&partnerID=8YFLogxK
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U2 - 10.2197/ipsjtsldm.5.96
DO - 10.2197/ipsjtsldm.5.96
M3 - Article
AN - SCOPUS:84864945815
SN - 1882-6687
VL - 5
SP - 96
EP - 105
JO - IPSJ Transactions on System LSI Design Methodology
JF - IPSJ Transactions on System LSI Design Methodology
ER -