A flexible multi-port RAM compiler for datapath

Hirofumi Shinohara; Noriaki Matsumoto; Kumiko Fujimori; Shuichi Kato

A flexible multi-port RAM compiler for datapath

Hirofumi Shinohara^*, Noriaki Matsumoto, Kumiko Fujimori, Shuichi Kato

^*この研究の対応する著者

研究成果: Conference article › 査読

10 被引用数 (Scopus)

抄録

A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.

本文言語	English
ジャーナル	Proceedings of the Custom Integrated Circuits Conference
出版ステータス	Published - 1990 12月 1
外部発表	はい
イベント	Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 - Boston, MA, USA 継続期間: 1990 5月 13 → 1990 5月 16

ASJC Scopus subject areas

電子工学および電気工学

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引用スタイル

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abstract = "A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.",

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year = "1990",

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AU - Shinohara, Hirofumi

AU - Matsumoto, Noriaki

AU - Fujimori, Kumiko

AU - Kato, Shuichi

PY - 1990/12/1

Y1 - 1990/12/1

N2 - A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.

AB - A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.

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M3 - Conference article

AN - SCOPUS:0025694010

SN - 0886-5930

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T2 - Proceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90

Y2 - 13 May 1990 through 16 May 1990

ER -

A flexible multi-port RAM compiler for datapath

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