A flexible multi-port RAM compiler for datapath

Hirofumi Shinohara*, Noriaki Matsumoto, Kumiko Fujimori, Shuichi Kato


研究成果: Conference article査読

10 被引用数 (Scopus)


A multiport RAM compiler with flexible layout and port-organization has been developed in an 1.0-μm CMOS technology. A novel memory cell scheme with an additional column enable gate yielded a controllability over the aspect ratio of the layout. This compiler generates up to 32K three-port RAM and 16K six-port RAM. Each port operates statically and asynchronously with each other port. The address access times of the generated three-port RAMs are 5.0 ns (1 kb) and 10.0 ns (32 kb), for example.

ジャーナルProceedings of the Custom Integrated Circuits Conference
出版ステータスPublished - 1990 12月 1
イベントProceedings of the 12th Annual IEEE 1990 Custom Integrated Circuits Conference - CICC '90 - Boston, MA, USA
継続期間: 1990 5月 131990 5月 16

ASJC Scopus subject areas

  • 電子工学および電気工学


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