A multiport RAM compiler with flexible layout and port organization has been developed using 1.0-μm CMOS technology. A new memory cell with an additional column-enable gate yielded a controllability over the aspect ratio of the memory cell array. Wide bit-word organization range including 2048 words × 16 b and 512 words × 72 b was also obtained. This compiler generates up to 32K three-port RAM and 16K six-port RAM. In addition to read and write ports, read/write ports are also available. The operations of the ports are fully static and asynchronous to each other. The RAM requires no dc power consumption. The address access times of the generated three-port RAM's are, for example, 5.0 ns for 1K and 11.0 ns for 32K.
|ジャーナル||IEEE Journal of Solid-State Circuits|
|出版ステータス||Published - 1991 3月|
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