A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability

Takeshi Hamamoto; Yoshihiro Minami; Tomoaki Shino; Naoki Kusunoki; Hiroomi Nakajima; Mutsuo Morikado; Takashi Yamada; Kazumi Inoh; Atsushi Sakamoto; Tomoki Higashi; Katsuyuki Fujita; Kozuke Hatsuda; Takashi Ohsawa; Akihiro Nitayama

doi:10.1109/TED.2006.890597

A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability

Takeshi Hamamoto^*, Yoshihiro Minami, Tomoaki Shino, Naoki Kusunoki, Hiroomi Nakajima, Mutsuo Morikado, Takashi Yamada, Kazumi Inoh, Atsushi Sakamoto, Tomoki Higashi, Katsuyuki Fujita, Kozuke Hatsuda, Takashi Ohsawa, Akihiro Nitayama

^*この研究の対応する著者

研究成果: Article › 査読

26 被引用数 (Scopus)

抄録

A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage.

本文言語	English
ページ（範囲）	563-571
ページ数	9
ジャーナル	IEEE Transactions on Electron Devices
巻	54
号	3
DOI	https://doi.org/10.1109/TED.2006.890597
出版ステータス	Published - 2007 3月
外部発表	はい

ASJC Scopus subject areas

電子材料、光学材料、および磁性材料
電子工学および電気工学

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10.1109/TED.2006.890597

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Hamamoto, T., Minami, Y., Shino, T., Kusunoki, N., Nakajima, H., Morikado, M., Yamada, T., Inoh, K., Sakamoto, A., Higashi, T., Fujita, K., Hatsuda, K., Ohsawa, T., & Nitayama, A. (2007). A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability. IEEE Transactions on Electron Devices, 54(3), 563-571. https://doi.org/10.1109/TED.2006.890597

Hamamoto, T, Minami, Y, Shino, T, Kusunoki, N, Nakajima, H, Morikado, M, Yamada, T, Inoh, K, Sakamoto, A, Higashi, T, Fujita, K, Hatsuda, K, Ohsawa, T & Nitayama, A 2007, 'A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability', IEEE Transactions on Electron Devices, vol. 54, no. 3, pp. 563-571. https://doi.org/10.1109/TED.2006.890597

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abstract = "A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage.",

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AU - Kusunoki, Naoki

AU - Nakajima, Hiroomi

AU - Morikado, Mutsuo

AU - Yamada, Takashi

AU - Inoh, Kazumi

AU - Sakamoto, Atsushi

AU - Higashi, Tomoki

AU - Fujita, Katsuyuki

AU - Hatsuda, Kozuke

AU - Ohsawa, Takashi

AU - Nitayama, Akihiro

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AB - A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) has been successfully developed for the first time. Two technologies have been newly implemented, namely: 1) the optimized well structure and 2) Cu wiring. The well design has been optimized both for the array device and the peripheral circuit in order to realize full functionality and good retention characteristics. Cu wiring has been used for the bit line and the source line, which increases the signal of the worst bit in the array and also realizes full compatibility with the standard CMOS process. Scalability of FBC down to 45-nm CMOS technology node has been investigated by a device simulation. The signal and the maximum electric field can be maintained constant with the reduction of the device dimensions and the operation voltage.

KW - DRAM chips

KW - Hot carriers

KW - MOSFETs

KW - Silicon-on-insulator (SOI) technology

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A floating-body cell fully compatible with 90-nm CMOS technology node for a 128-Mb SOI DRAM and its scalability

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