A floorplan-aware high-level synthesis technique with delay-variation tolerance

Keyphrases

• Floorplanning 100%
• Synthesis Methods 100%
• High-level Synthesis 100%
• Delay Variation 100%
• Variation Tolerance 100%
• Interconnect Delay 50%
• Performance Overhead 25%
• Yield Rate 25%
• Latency 25%
• Small Area 25%
• Post-silicon 25%
• LSI Design 25%
• Performance Rate 25%

Computer Science

• High Level Synthesis 100%
• Delay Variation 100%
• Synthesis Technique 100%
• Interconnect Delay 50%
• Experimental Result 25%
• Driven Architecture 25%