As process technologies advance, interconnection delays are not negligible even in high-level synthesis and regular-distributed-register (RDR) architecture has been proposed to cope with this problem. In this paper, we propose a floorplan-driven high-level synthesis algorithm using multiple-operation chainings composed of two or more operations, and reduce the overall latency targeting RDR architecture. Our algorithm enumerates multiple-operation-chaining path candidates before performing scheduling/binding. Based on them, we find out optimal ones taking into account RDR floorplan information. Experimental results show that our algorithm successfully reduces the latency by up to 30.4% compared to the conventional approaches.
|Proceedings - IEEE International Symposium on Circuits and Systems
|Institute of Electrical and Electronics Engineers Inc.
|Published - 2015 7月 27
|IEEE International Symposium on Circuits and Systems, ISCAS 2015 - Lisbon, Portugal
継続期間: 2015 5月 24 → 2015 5月 27
|IEEE International Symposium on Circuits and Systems, ISCAS 2015
|15/5/24 → 15/5/27
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