TY - GEN
T1 - A FPGA-based real-time hardware accelerator for orientation calculation part in SIFT
AU - Qiu, Jingbang
AU - Lu, Ying
AU - Huang, Tianci
AU - Ikenaga, Takeshi
PY - 2009/12/1
Y1 - 2009/12/1
N2 - SIFT is regarded as one of the most powerful feature point detection algorithms in the world. The Orientation Calculation Part, defining major orientation of feature points, enables selected image features to be invariant to rotation changes. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing LUT-Based Square Root Computation and Shifting-Based Orientation Calculation with use of dual-port DDR2 memory access, we achieve to reach real-time process speed, meanwhile keeping high accuracy. By experiment, our system proves to reach Max Clock Frequency of 130.0 MHz, processing up to around 256,000 feature points including memory operations. Compared with conventional work, hardware cost is remained at the same level. Accuracy is kept at 98.9% for over 40,000 feature points from 50 images. Our proposal is suitable for a real-time SIFT system.
AB - SIFT is regarded as one of the most powerful feature point detection algorithms in the world. The Orientation Calculation Part, defining major orientation of feature points, enables selected image features to be invariant to rotation changes. In this paper, we propose an FPGA-implementable hardware accelerator for this part. By introducing LUT-Based Square Root Computation and Shifting-Based Orientation Calculation with use of dual-port DDR2 memory access, we achieve to reach real-time process speed, meanwhile keeping high accuracy. By experiment, our system proves to reach Max Clock Frequency of 130.0 MHz, processing up to around 256,000 feature points including memory operations. Compared with conventional work, hardware cost is remained at the same level. Accuracy is kept at 98.9% for over 40,000 feature points from 50 images. Our proposal is suitable for a real-time SIFT system.
UR - http://www.scopus.com/inward/record.url?scp=73649110590&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=73649110590&partnerID=8YFLogxK
U2 - 10.1109/IIH-MSP.2009.64
DO - 10.1109/IIH-MSP.2009.64
M3 - Conference contribution
AN - SCOPUS:73649110590
SN - 9780769537627
T3 - IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing
SP - 1334
EP - 1337
BT - IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing
T2 - IIH-MSP 2009 - 2009 5th International Conference on Intelligent Information Hiding and Multimedia Signal Processing
Y2 - 12 September 2009 through 14 September 2009
ER -