抄録
In this paper, we propose a generalized V-shaped multilevel floorplanning method with consideration of fixedoutline constraint. The Sequence Pair is used as the floorplan representation. The proposed multilevel method (ML-IARFP) adopts a two-stage structure: top-down partitioning and floorplanning followed by bottom-up merging and refinement. At the first stage, we recursively partition and floorplan the circuits until there are limited number blocks in each sub-circuit. Since we use a multi-partitioning instead of bi-partitioning, general non-slicing floorplan structures are explored in each level, which potentially lead to more effective exploration of the solution space. At the second stage, using a multilevel sequence pair structure, we recursively merge the sub-circuits into bigger circuits and do the refinement. Compared with IMF, Capo 10.2 and IARFP, MLIARFP obtained the best results under fixed-outline constraints, and compared with IARFP, it achieved 9% wirelength reduction on average and showed a better scalability.
本文言語 | English |
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ホスト出版物のタイトル | Proceedings of the 10th International Symposium on Quality Electronic Design, ISQED 2009 |
ページ | 734-739 |
ページ数 | 6 |
DOI | |
出版ステータス | Published - 2009 |
イベント | 10th International Symposium on Quality Electronic Design, ISQED 2009 - San Jose, CA 継続期間: 2009 3月 16 → 2009 3月 18 |
Other
Other | 10th International Symposium on Quality Electronic Design, ISQED 2009 |
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City | San Jose, CA |
Period | 09/3/16 → 09/3/18 |
ASJC Scopus subject areas
- ハードウェアとアーキテクチャ
- 電子工学および電気工学