TY - JOUR
T1 - A GIDL-current model for advanced MOSFET technologies without binning
AU - Inagaki, Ryosuke
AU - Sadachika, Norio
AU - Navarro, Dondee
AU - Miura-Mattausch, Mitiko
AU - Inoue, Yasuaki
PY - 2009
Y1 - 2009
N2 - A GIDL (Gate Induced Drain Leakage) current model for advanced MOS-FETs is proposed and implemented into HiSIM2, complete surface potential based MOSFET model. The model considers two tunneling mechanisms, the band-to-band tunneling and the trap assisted tunneling. Totally 7 model parameters are introduced. Simulation results of NFETs and PFETs reproduce measurements for any device size without binning of model parameters. The influence of the GIDL current is investigated with circuits, which are sensitive to the change of the stored charge due to the GIDL current.
AB - A GIDL (Gate Induced Drain Leakage) current model for advanced MOS-FETs is proposed and implemented into HiSIM2, complete surface potential based MOSFET model. The model considers two tunneling mechanisms, the band-to-band tunneling and the trap assisted tunneling. Totally 7 model parameters are introduced. Simulation results of NFETs and PFETs reproduce measurements for any device size without binning of model parameters. The influence of the GIDL current is investigated with circuits, which are sensitive to the change of the stored charge due to the GIDL current.
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U2 - 10.2197/ipsjtsldm.2.93
DO - 10.2197/ipsjtsldm.2.93
M3 - Article
AN - SCOPUS:79954520751
SN - 1882-6687
VL - 2
SP - 93
EP - 102
JO - IPSJ Transactions on System LSI Design Methodology
JF - IPSJ Transactions on System LSI Design Methodology
ER -