TY - GEN
T1 - A hardware/software partitioning algorithm for processor cores of digital signal processing
AU - Togawa, Nozomu
AU - Sakurai, Takashi
AU - Yanagisawa, Masao
AU - Ohtsuki, Tatsuo
N1 - Funding Information:
The authors would like to thank M. Hamabe, T. Kawasaki, A. Nose, T. Nakamura, Y. Kataoka, and D. Yoshizawa of Waseda University for their implementations and valuable discussions.
Publisher Copyright:
© 1999 Institute of Electrical and Electronics Engineers Inc.. All rights reserved.
PY - 1999
Y1 - 1999
N2 - A hardware/software cosynthesis system for processor cores of digital signal processing has been developed. This paper focuses on a hardware/software partitioning algorithm which is one of the key issues in the system. Given an input assembly code generated by the compiler in the system, the proposed hardware/software partitioning algorithm first determines the types and the numbers of required hardware units, such as multiple functional units, hardware loop units, and particular addressing units, for a processor core (initial resource allocation). Second, the hardware units determined at initial resource allocation are reduced one by one while the assembly code meets a given timing constraint (configuration of a processor core). The execution time of the assembly code becomes longer but the hardware costs for a processor core to execute it becomes smaller. Finally, it outputs an optimized assembly code and a processor configuration. Experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program/data.
AB - A hardware/software cosynthesis system for processor cores of digital signal processing has been developed. This paper focuses on a hardware/software partitioning algorithm which is one of the key issues in the system. Given an input assembly code generated by the compiler in the system, the proposed hardware/software partitioning algorithm first determines the types and the numbers of required hardware units, such as multiple functional units, hardware loop units, and particular addressing units, for a processor core (initial resource allocation). Second, the hardware units determined at initial resource allocation are reduced one by one while the assembly code meets a given timing constraint (configuration of a processor core). The execution time of the assembly code becomes longer but the hardware costs for a processor core to execute it becomes smaller. Finally, it outputs an optimized assembly code and a processor configuration. Experimental results demonstrate that the system synthesizes processor cores effectively according to the features of an application program/data.
UR - http://www.scopus.com/inward/record.url?scp=85027107562&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=85027107562&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.1999.760027
DO - 10.1109/ASPDAC.1999.760027
M3 - Conference contribution
AN - SCOPUS:85027107562
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 335
EP - 338
BT - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 1999
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 4th Asia and South Pacific Design Automation Conference, ASP-DAC 1999
Y2 - 18 January 1999 through 21 January 1999
ER -