TY - GEN
T1 - A hardware/software partitioning algorithm for SIMD processor cores
AU - Tachikake, K.
AU - Togawa, N.
AU - Miyaoka, Y.
AU - Choi, Jinku
AU - Yanagisawa, M.
AU - Ohtsuki, T.
N1 - Publisher Copyright:
© 2003 IEEE.
PY - 2003
Y1 - 2003
N2 - This paper proposes a new hardware/software partitioning algorithm for processor cores with SIMD instructions. Given a compiled assembly code including SIMD instructions, a timing constraint of execution time, and available hardware units, the proposed algorithm synthesizes an area-optimized processor core with a new assembly code. Firstly, we assume an initial processor core on which an input assembly code can run with the shortest execution time. Secondly we reduce a hardware unit added to a processor core one by one while the timing constraint is satisfied. At the same time, we update the assembly code so that it can run on the new processor configuration. By repeating this process, we finally obtain a processor core architecture with small area under the given timing constraint. We expect that vie can obtain a processor core which has appropriate SIMD functional units for running the input application program. The promising experimental results are also shown.
AB - This paper proposes a new hardware/software partitioning algorithm for processor cores with SIMD instructions. Given a compiled assembly code including SIMD instructions, a timing constraint of execution time, and available hardware units, the proposed algorithm synthesizes an area-optimized processor core with a new assembly code. Firstly, we assume an initial processor core on which an input assembly code can run with the shortest execution time. Secondly we reduce a hardware unit added to a processor core one by one while the timing constraint is satisfied. At the same time, we update the assembly code so that it can run on the new processor configuration. By repeating this process, we finally obtain a processor core architecture with small area under the given timing constraint. We expect that vie can obtain a processor core which has appropriate SIMD functional units for running the input application program. The promising experimental results are also shown.
UR - http://www.scopus.com/inward/record.url?scp=2442491893&partnerID=8YFLogxK
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U2 - 10.1109/ASPDAC.2003.1195006
DO - 10.1109/ASPDAC.2003.1195006
M3 - Conference contribution
AN - SCOPUS:2442491893
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 135
EP - 140
BT - Proceedings of the ASP-DAC 2003 Asia and South Pacific Design Automation Conference
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - Asia and South Pacific Design Automation Conference, ASP-DAC 2003
Y2 - 21 January 2003 through 24 January 2003
ER -