A high assurance on-line recovery technology for a space on-board computer

Hiroyuki Yashiro*, Teruo Fujiwara, Kinji Mori

*この研究の対応する著者

研究成果: Article査読

1 被引用数 (Scopus)

抄録

A high assurance on-line recovery technology for a space on-board computer that can be realized using commercial devices is proposed whereby a faulty processor node confirms its normality and then recovers without affecting the other processor nodes in operation. Also, the result of an evaluation test using the broadboard model implementing this technology is reported. Because this technology enables simple and assured recovery of a faulty processor node regardless of its degree of redundancy, it can be applied to various applications, such as a launch vehicle, a satellite, and a reusable launch vehicle. As a result, decreasing the cost of an on-board computer is possible while maintaining its high reliability.

本文言語English
ページ(範囲)1350-1359
ページ数10
ジャーナルIEICE Transactions on Information and Systems
E84-D
10
出版ステータスPublished - 2001 10月
外部発表はい

ASJC Scopus subject areas

  • 情報システム
  • コンピュータ グラフィックスおよびコンピュータ支援設計
  • ソフトウェア

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