A high-level synthesis algorithm for FPGA designs optimizing critical path with interconnection-delay and clock-skew consideration

Koichi Fujiwara, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

研究成果: Conference contribution

4 被引用数 (Scopus)

抄録

High-level synthesis for FPGA designs (FPGA-HLS) is recently required in various applications. Since wire delays are becoming a design bottleneck in FPGA, we need to handle interconnection delays and clock skews in FPGA-HLS flow. In this paper, we propose an FPGA-HLS algorithm optimizing critical path with interconnection-delay and clock-skew consideration. By utilizing HDR architecture, we floorplan circuit modules in HLS flow and, based on the result, estimate interconnection delays and clock skews. To reduce the critical-path delay(s) of a circuit, we propose two novel methods for FPGA-HLS. Experimental results demonstrate that our algorithm can improve circuit performance by up to 24% compared with conventional approaches.

本文言語English
ホスト出版物のタイトル2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
出版社Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）9781467394987
DOI
出版ステータスPublished - 2016 5月 31
イベント2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016 - Hsinchu, Taiwan, Province of China
継続期間: 2016 4月 25 → 2016 4月 27

出版物シリーズ

名前2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016

Other

Other2016 International Symposium on VLSI Design, Automation and Test, VLSI-DAT 2016
国/地域Taiwan, Province of China
CityHsinchu
Period16/4/25 → 16/4/27

ASJC Scopus subject areas

  • ハードウェアとアーキテクチャ
  • 電子工学および電気工学
  • 安全性、リスク、信頼性、品質管理
  • 器械工学

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