TY - GEN
T1 - A high performance LDPC decoder for IEEE802.11n standard
AU - Jit, Wen
AU - Abe, Yuta
AU - Ikenaga, Takeshi
AU - Goto, Satoshi
PY - 2009/4/20
Y1 - 2009/4/20
N2 - In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.
AB - In this paper, we propose a partially-parallel irregular LDPC decoder for IEEE 802.11n standard. The design is based on a novel sum-delta message passing schedule to achieve high throughput and low area cost design. We further improve the design with pipeline structure and parallel computation. The synthesis result in TSMC 0.18 CMOS technology demonstrates that for (648,324) irregular LDPC code, our decoder achieves 7.5X improvement in throughput, which reaches 402 Mbps at the frequency of 200MHz, with 11% area reduction.
UR - http://www.scopus.com/inward/record.url?scp=64549145025&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=64549145025&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2009.4796465
DO - 10.1109/ASPDAC.2009.4796465
M3 - Conference contribution
AN - SCOPUS:64549145025
SN - 9781424427482
T3 - Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
SP - 127
EP - 128
BT - Proceedings of the ASP-DAC 2009
T2 - Asia and South Pacific Design Automation Conference 2009, ASP-DAC 2009
Y2 - 19 January 2009 through 22 January 2009
ER -