A high random-access-data-rate 4MbDRAM with pipeline operation

Tohru Furuyama; Natsuki Kushiyama; Yohji Watanabe; Takashi Ohsawa; Kazuyoshi Muraoka; Yousei Nagahama

A high random-access-data-rate 4MbDRAM with pipeline operation

Tohru Furuyama^*, Natsuki Kushiyama, Yohji Watanabe, Takashi Ohsawa, Kazuyoshi Muraoka, Yousei Nagahama

^*この研究の対応する著者

研究成果: Paper › 査読

3 被引用数 (Scopus)

抄録

A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.

本文言語	English
ページ	9-10
ページ数	2
出版ステータス	Published - 1990 12月 1
外部発表	はい
イベント	1990 Symposium on VLSI Circuits - Honolulu, HI, USA 継続期間: 1990 6月 7 → 1990 6月 9

Other

Other	1990 Symposium on VLSI Circuits
City	Honolulu, HI, USA
Period	90/6/7 → 90/6/9

ASJC Scopus subject areas

工学（全般）

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引用スタイル

@conference{f2f6e036166f466993fe10b8748e7a9d,

title = "A high random-access-data-rate 4MbDRAM with pipeline operation",

abstract = "A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.",

author = "Tohru Furuyama and Natsuki Kushiyama and Yohji Watanabe and Takashi Ohsawa and Kazuyoshi Muraoka and Yousei Nagahama",

year = "1990",

month = dec,

day = "1",

language = "English",

pages = "9--10",

note = "1990 Symposium on VLSI Circuits ; Conference date: 07-06-1990 Through 09-06-1990",

}

TY - CONF

T1 - A high random-access-data-rate 4MbDRAM with pipeline operation

AU - Furuyama, Tohru

AU - Kushiyama, Natsuki

AU - Watanabe, Yohji

AU - Ohsawa, Takashi

AU - Muraoka, Kazuyoshi

AU - Nagahama, Yousei

PY - 1990/12/1

Y1 - 1990/12/1

N2 - A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.

AB - A novel circuit technology which introduces a pipeline scheme in a read operation and improves the random-access data rate by roughly 30% is described. This technology has been applied to a 4M DRAM, and the RAM showed a short cycle time of less than 100 ns, i.e., a more than 10-MHz data rate, under the worst operating condition. In addition, a very fast virtual RAS access time of 20 ns has been obtained. Since the pipeline DRAM does not require any new process and/or assembly technologies, it can be added to the standard DRAM family.

UR - http://www.scopus.com/inward/record.url?scp=0025551435&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0025551435&partnerID=8YFLogxK

M3 - Paper

AN - SCOPUS:0025551435

SP - 9

EP - 10

T2 - 1990 Symposium on VLSI Circuits

Y2 - 7 June 1990 through 9 June 1990

ER -

A high random-access-data-rate 4MbDRAM with pipeline operation

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Other

ASJC Scopus subject areas

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