This paper presents a VLSI implementation for inverse transforms of H.264/AVC, AVS and MPEG1/2/4. Based on distributed arithmetic, the inverse transforms of the three video coding standards share the unique architecture, which achieves less hardware cost and better decoding efficiency than separate designs. The core element of the distributed arithmetic is implemented with pipelined architecture, where only table accessing, shift and accumulation are needed. To optimize the efficiency ofinverse transformation, a zero pre-detecting scheme is used in the proposed architecture. The distributed arithmetic tables are organized as differential code to reduce almost half of the ROM size. With our dedicated modularization, the proposed architecture is suitable for multi-standard HDTV applications.
|ホスト出版物のタイトル||ASICON 2009 - Proceedings 2009 8th IEEE International Conference on ASIC|
|出版ステータス||Published - 2009|
|イベント||2009 8th IEEE International Conference on ASIC, ASICON 2009 - Changsha|
継続期間: 2009 10月 20 → 2009 10月 23
|Other||2009 8th IEEE International Conference on ASIC, ASICON 2009|
|Period||09/10/20 → 09/10/23|
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