TY - GEN
T1 - A hybrid architecture for efficient FPGA-based implementation of multilayer neural network
AU - Lin, Zhen
AU - Dong, Yiping
AU - Li, Yan
AU - Watanabe, Takahiro
PY - 2010/12/1
Y1 - 2010/12/1
N2 - This paper presents a novel architecture for the FPGA-based implementation of multilayer neural network (NN), which integrates the layer-multiplexing and pipeline architecture together. The proposed method is aimed at enhancing the efficiency of resource usage and improving the forward speed at the module level, so that a larger NN can be implemented on commercial FPGAs. We developed a mapping method from NN schematic to physical architecture in FPGA by using the hybrid architecture, and also developed an algorithm to automatically determine the architecture by optimizing the application specific neural network topology. The experimental results with several different network topologies show that the proposed architecture can produce a very compact circuit with higher speed, compared with conventional methods.
AB - This paper presents a novel architecture for the FPGA-based implementation of multilayer neural network (NN), which integrates the layer-multiplexing and pipeline architecture together. The proposed method is aimed at enhancing the efficiency of resource usage and improving the forward speed at the module level, so that a larger NN can be implemented on commercial FPGAs. We developed a mapping method from NN schematic to physical architecture in FPGA by using the hybrid architecture, and also developed an algorithm to automatically determine the architecture by optimizing the application specific neural network topology. The experimental results with several different network topologies show that the proposed architecture can produce a very compact circuit with higher speed, compared with conventional methods.
UR - http://www.scopus.com/inward/record.url?scp=79959216420&partnerID=8YFLogxK
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U2 - 10.1109/APCCAS.2010.5774961
DO - 10.1109/APCCAS.2010.5774961
M3 - Conference contribution
AN - SCOPUS:79959216420
SN - 9781424474561
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 616
EP - 619
BT - Proceedings of the 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
T2 - 2010 Asia Pacific Conference on Circuit and System, APCCAS 2010
Y2 - 6 December 2010 through 9 December 2010
ER -