TY - GEN
T1 - A hybrid NoC architecture utilizing packet transmission priority control method
AU - Lee, Seungju
AU - Togawa, Nozomu
AU - Sekihara, Yusuke
AU - Aoki, Takashi
AU - Onozawa, Akira
PY - 2012
Y1 - 2012
N2 - Network-on-chip architectures have emerged as a promising solution to the lack of scalability in multi-processor systems-on-chips (MPSoCs). With the explosive growth in the usage of multimedia applications, it is expected that NoC serves as a multimedia server supporting multi-class services. Recently, a busmesh NoC (BMNoC) has been proposed. The BMNoC architecture, which analyses the data traffic and makes aware of localities between cores, improves the system performance in terms of latency as compared with conventional NoCs. In this paper, we propose a novel BMNoC utilizing packet transmission priority control methods. Our proposed BMNoC is a generalized and simplified version of a hybrid NoC which is composed of local buses and global mesh routers. Several realistic applications applied to our algorithm illustrate the better performance than previous studies and feasibility of our proposed architecture.
AB - Network-on-chip architectures have emerged as a promising solution to the lack of scalability in multi-processor systems-on-chips (MPSoCs). With the explosive growth in the usage of multimedia applications, it is expected that NoC serves as a multimedia server supporting multi-class services. Recently, a busmesh NoC (BMNoC) has been proposed. The BMNoC architecture, which analyses the data traffic and makes aware of localities between cores, improves the system performance in terms of latency as compared with conventional NoCs. In this paper, we propose a novel BMNoC utilizing packet transmission priority control methods. Our proposed BMNoC is a generalized and simplified version of a hybrid NoC which is composed of local buses and global mesh routers. Several realistic applications applied to our algorithm illustrate the better performance than previous studies and feasibility of our proposed architecture.
UR - http://www.scopus.com/inward/record.url?scp=84874154142&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84874154142&partnerID=8YFLogxK
U2 - 10.1109/APCCAS.2012.6419057
DO - 10.1109/APCCAS.2012.6419057
M3 - Conference contribution
AN - SCOPUS:84874154142
SN - 9781457717291
T3 - IEEE Asia-Pacific Conference on Circuits and Systems, Proceedings, APCCAS
SP - 404
EP - 407
BT - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
T2 - 2012 IEEE Asia Pacific Conference on Circuits and Systems, APCCAS 2012
Y2 - 2 December 2012 through 5 December 2012
ER -