TY - GEN
T1 - A length matching routing method for disordered pins in PCB design
AU - Zhang, Ran
AU - Pan, Tieyuan
AU - Zhu, Li
AU - Watanabe, Takahiro
N1 - Publisher Copyright:
© 2015 IEEE.
PY - 2015/3/11
Y1 - 2015/3/11
N2 - In this paper, for the disordered pins in printed circuit board (PCB) design, a heuristics algorithm is proposed to obtain a length matching routing. We initially check the longest common subsequence of pin pairs to assign layers for pins. Then, adopt single commodity flow to generate base routes. R-flip and C-flip are finally carried out to adjust the wire length. The experiments show that our algorithm generates the optimal routes with better wire balance within reasonable CPU times.
AB - In this paper, for the disordered pins in printed circuit board (PCB) design, a heuristics algorithm is proposed to obtain a length matching routing. We initially check the longest common subsequence of pin pairs to assign layers for pins. Then, adopt single commodity flow to generate base routes. R-flip and C-flip are finally carried out to adjust the wire length. The experiments show that our algorithm generates the optimal routes with better wire balance within reasonable CPU times.
UR - http://www.scopus.com/inward/record.url?scp=84926469169&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84926469169&partnerID=8YFLogxK
U2 - 10.1109/ASPDAC.2015.7059038
DO - 10.1109/ASPDAC.2015.7059038
M3 - Conference contribution
AN - SCOPUS:84926469169
T3 - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
SP - 402
EP - 407
BT - 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
PB - Institute of Electrical and Electronics Engineers Inc.
T2 - 2015 20th Asia and South Pacific Design Automation Conference, ASP-DAC 2015
Y2 - 19 January 2015 through 22 January 2015
ER -