@article{4837d68765214e57bee81a53006bfcea,
title = "A Low-Cost Training Method of ReRAM Inference Accelerator Chips for Binarized Neural Networks to Recover Accuracy Degradation due to Statistical Variabilities",
abstract = "A new software based in-situ training (SBIST) method to achieve high accuracies is proposed for binarized neural networks inference accelerator chips in which measured offsets in sense amplifiers (activation binarizers) are transformed into biases in the training software. To expedite this individual training, the initial values for the weights are taken from results of a common forming training process which is conducted in advance by using the offset fluctuation distribution averaged over the fabrication line. SPICE simulation inference results for the accelerator predict that the accuracy recovers to higher than 90% even when the amplifier offset is as large as 40mV only after a few epochs of the individual training.",
keywords = "binarized neural networks (BNNs), deep neural networks (DNNs), fabrication fluctuation, in-memory computing, in-situ training, ReRAM",
author = "Zian Chen and Takashi Ohsawa",
note = "Funding Information: This work partly executed under the cooperation of organization between Kioxia Corporation and Waseda University. This work was supported by JSPS KAKENHI Grant Number JP20K04626. This work was also supported by VLSI Design and Education Center (VDEC), the University of Tokyo with the collaboration with Synopsys Corporation. Publisher Copyright: Copyright {\textcopyright} 2022 The Institute of Electronics, Information and Communication Engineers.",
year = "2022",
month = aug,
doi = "10.1587/transele.2021ECP5040",
language = "English",
volume = "E105.C",
pages = "375--384",
journal = "IEICE Transactions on Electronics",
issn = "0916-8524",
publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",
number = "8",
}