A low-power soft error tolerant latch scheme

Saki Tajima; Youhua Shi; Nozomu Togawa; Masao Yanagisawa

doi:10.1109/ASICON.2015.7516885

A low-power soft error tolerant latch scheme

Saki Tajima, Youhua Shi, Nozomu Togawa, Masao Yanagisawa

研究成果: Conference contribution

1 被引用数 (Scopus)

抄録

As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.

本文言語	English
ホスト出版物のタイトル	Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015
出版社	Institute of Electrical and Electronics Engineers Inc.
ISBN（電子版）	9781479984831
DOI	https://doi.org/10.1109/ASICON.2015.7516885
出版ステータス	Published - 2016 7月 19
イベント	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015 - Chengdu, China 継続期間: 2015 11月 3 → 2015 11月 6

Other

Other	11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015
国/地域	China
City	Chengdu
Period	15/11/3 → 15/11/6

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学

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10.1109/ASICON.2015.7516885

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引用スタイル

Tajima, S, Shi, Y , Togawa, N & Yanagisawa, M 2016, A low-power soft error tolerant latch scheme. in Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015., 7516885, Institute of Electrical and Electronics Engineers Inc., 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015, Chengdu, China, 15/11/3. https://doi.org/10.1109/ASICON.2015.7516885

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abstract = "As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.",

author = "Saki Tajima and Youhua Shi and Nozomu Togawa and Masao Yanagisawa",

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N2 - As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.

AB - As process technology continues scaling, low power and reliability of integrated circuits are becoming more critical than ever before. Particularly, due to the reduction of node capacitance and operating voltage for low power consumption, it makes the circuits more sensitive to high-energy particles induced soft errors. In this paper, a soft-error tolerant latch called TSPC-SEH is proposed for soft error tolerance with low power consumption. The simulation results show that the proposed TSPC-SEH latch can achieve up to 42% power consumption reduction and 54% delay improvement compared to the existing soft error tolerant SEH and DICE designs.

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T2 - 11th IEEE International Conference on Advanced Semiconductor Integrated Circuits (ASIC), ASICON 2015

Y2 - 3 November 2015 through 6 November 2015

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A low-power soft error tolerant latch scheme

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