抄録
A new architecture for the NVRAM suitable to highdensity applications is described. In the new cell, a dynamic RAM cell is merged into an EEPROM cell. A capacitor is made between the control gate and the drain diffusion layer of the FLOTOX-type EEPROM memory cell. The equivalent circuit in the dynamic RAM mode consists of two transistors and a capacitor, which eliminates a dummy cell. A dynamic RAM sense amplifier is used in both modes, and it works as a data latch when data are transferred between the dynamic RAM part and the EEPROM part. The process of the NVRAM is compatible with ordinary EEPROM's.
| 本文言語 | English |
|---|---|
| ページ（範囲） | 86-90 |
| ページ数 | 5 |
| ジャーナル | IEEE Journal of Solid-State Circuits |
| 巻 | 23 |
| 号 | 1 |
| DOI | |
| 出版ステータス | Published - 1988 |
| 外部発表 | はい |
ASJC Scopus subject areas
- 電子工学および電気工学