抄録
In this paper a new low power BIST methodology by altering the structure of linear feedback shift register (LFSR) is proposed. In pseudo-random test mode, the efficiency of the vectors decreases sharply as the test progresses. For low power consumption during test mode, the proposed approach ignores the non-detecting vectors by altering the structure of LFSR. Note that altering the structure of LFSR is efficient, and its has no impact on the fault coverage.
本文言語 | English |
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ページ | 646-649 |
ページ数 | 4 |
出版ステータス | Published - 2001 |
外部発表 | はい |
イベント | 4th International Conference on ASIC Proceedings - Shanghai, China 継続期間: 2001 10月 23 → 2001 10月 25 |
Conference
Conference | 4th International Conference on ASIC Proceedings |
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国/地域 | China |
City | Shanghai |
Period | 01/10/23 → 01/10/25 |
ASJC Scopus subject areas
- 工学(全般)