A new self-test structure for at-speed test of crosstalk in SoC busses

The use of deep submicron process technologies increases the probability of crosstalk faults in the bus of system-on-a-chip (SoC). Though a self-testing methodology based on MA fault model has been developed, its area overhead of test logic is excessive. This paper proposed a new Error Detector (ED) and new test patterns whose overhead is decreased down to only approximate 50% of the old methodology on the average. A behavior fault simulation is used to validate the self-testing structure described in this paper.