A new software for test logic optimization in DFT

Zhe Zhang; Chen Hu; Rui Li; Youhua Shi; Longxing Shi

A new software for test logic optimization in DFT

Zhe Zhang^*, Chen Hu, Rui Li, Youhua Shi, Longxing Shi

^*この研究の対応する著者

研究成果: Paper › 査読

1 被引用数 (Scopus)

抄録

This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.

本文言語	English
ページ	654-657
ページ数	4
出版ステータス	Published - 2001
外部発表	はい
イベント	4th International Conference on ASIC Proceedings - Shanghai, China 継続期間: 2001 10月 23 → 2001 10月 25

Conference

Conference	4th International Conference on ASIC Proceedings
国/地域	China
City	Shanghai
Period	01/10/23 → 01/10/25

ASJC Scopus subject areas

工学（全般）

他のファイルとリンク

引用スタイル

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title = "A new software for test logic optimization in DFT",

abstract = "This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.",

author = "Zhe Zhang and Chen Hu and Rui Li and Youhua Shi and Longxing Shi",

year = "2001",

language = "English",

pages = "654--657",

note = "4th International Conference on ASIC Proceedings ; Conference date: 23-10-2001 Through 25-10-2001",

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TY - CONF

T1 - A new software for test logic optimization in DFT

AU - Zhang, Zhe

AU - Hu, Chen

AU - Li, Rui

AU - Shi, Youhua

AU - Shi, Longxing

PY - 2001

Y1 - 2001

N2 - This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.

AB - This paper presents a new software named ASIC2000TA developed for design for test (DFT) aiming at optimizing test logic. This software consists of two modules: Test analysis module and DFT module. Test analysis module can examine circuit's testability, generate test vectors and perform fault simulation, in which some algorithms are described. DFT module automatically inserts test logic in gate-level netlist, including full scan and partial scan, in which a greedy search algorithm is discussed. Electronic design intermediate format (EDIF) acts as an interface between ASIC2000TA and Cadence. An experiment of ASIC2000TA is presented at last.

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M3 - Paper

AN - SCOPUS:0035719450

SP - 654

EP - 657

T2 - 4th International Conference on ASIC Proceedings

Y2 - 23 October 2001 through 25 October 2001

ER -

A new software for test logic optimization in DFT

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Conference

ASJC Scopus subject areas

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