A pipeline parallel tree architecture for full search variable block size motion estimation in H.264/AVC

Zhenyu Liu; Yang Song; Takeshi Ikenaga; Satoshi Goto

A pipeline parallel tree architecture for full search variable block size motion estimation in H.264/AVC

Zhenyu Liu^*, Yang Song, Takeshi Ikenaga, Satoshi Goto

^*この研究の対応する著者

大学院情報生産システム研究科

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

A fine-grain scalable parallel tree architecture for full search variable block size motion estimation (VBSME) with integer pixel accuracy is proposed in this paper. Through exploiting the spatial data correlations between horizontal candidate block searches, m×16 process elements (PE) are scheduled to work in parallel and fully utilized. The basic extension grain is one process element group (PEG), which accounts for 16 PE and 8.5K gates. In this architecture, the search window memory partition number is largely reduced. Consequently no trivial hardware cost and power consumption can be saved. One 16-PEG design with 48×32 search range has been implemented with TSMC 0.18μm CMOS technology. The core area is 1717μm×1713μm and the clock frequency is 261MHz in typical working condition.

本文言語	English
ホスト出版物のタイトル	25th PCS Proceedings
ホスト出版物のサブタイトル	Picture Coding Symposium 2006, PCS2006
出版ステータス	Published - 2006 12月 1
イベント	25th PCS: Picture Coding Symposium 2006, PCS2006 - Beijing, China 継続期間: 2006 4月 24 → 2006 4月 26

出版物シリーズ

名前	25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006
巻	2006

Conference

Conference	25th PCS: Picture Coding Symposium 2006, PCS2006
国/地域	China
City	Beijing
Period	06/4/24 → 06/4/26

ASJC Scopus subject areas

工学（全般）

他のファイルとリンク

引用スタイル

@inproceedings{5425d176d1854f31954ef402acef1c1c,

title = "A pipeline parallel tree architecture for full search variable block size motion estimation in H.264/AVC",

abstract = "A fine-grain scalable parallel tree architecture for full search variable block size motion estimation (VBSME) with integer pixel accuracy is proposed in this paper. Through exploiting the spatial data correlations between horizontal candidate block searches, m×16 process elements (PE) are scheduled to work in parallel and fully utilized. The basic extension grain is one process element group (PEG), which accounts for 16 PE and 8.5K gates. In this architecture, the search window memory partition number is largely reduced. Consequently no trivial hardware cost and power consumption can be saved. One 16-PEG design with 48×32 search range has been implemented with TSMC 0.18μm CMOS technology. The core area is 1717μm×1713μm and the clock frequency is 261MHz in typical working condition.",

keywords = "H.264/AVC, VLSI architecture, Variable block size motion estimation",

author = "Zhenyu Liu and Yang Song and Takeshi Ikenaga and Satoshi Goto",

year = "2006",

month = dec,

day = "1",

language = "English",

isbn = "300018726X",

series = "25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006",

booktitle = "25th PCS Proceedings",

note = "25th PCS: Picture Coding Symposium 2006, PCS2006 ; Conference date: 24-04-2006 Through 26-04-2006",

}

TY - GEN

T1 - A pipeline parallel tree architecture for full search variable block size motion estimation in H.264/AVC

AU - Liu, Zhenyu

AU - Song, Yang

AU - Ikenaga, Takeshi

AU - Goto, Satoshi

PY - 2006/12/1

Y1 - 2006/12/1

N2 - A fine-grain scalable parallel tree architecture for full search variable block size motion estimation (VBSME) with integer pixel accuracy is proposed in this paper. Through exploiting the spatial data correlations between horizontal candidate block searches, m×16 process elements (PE) are scheduled to work in parallel and fully utilized. The basic extension grain is one process element group (PEG), which accounts for 16 PE and 8.5K gates. In this architecture, the search window memory partition number is largely reduced. Consequently no trivial hardware cost and power consumption can be saved. One 16-PEG design with 48×32 search range has been implemented with TSMC 0.18μm CMOS technology. The core area is 1717μm×1713μm and the clock frequency is 261MHz in typical working condition.

AB - A fine-grain scalable parallel tree architecture for full search variable block size motion estimation (VBSME) with integer pixel accuracy is proposed in this paper. Through exploiting the spatial data correlations between horizontal candidate block searches, m×16 process elements (PE) are scheduled to work in parallel and fully utilized. The basic extension grain is one process element group (PEG), which accounts for 16 PE and 8.5K gates. In this architecture, the search window memory partition number is largely reduced. Consequently no trivial hardware cost and power consumption can be saved. One 16-PEG design with 48×32 search range has been implemented with TSMC 0.18μm CMOS technology. The core area is 1717μm×1713μm and the clock frequency is 261MHz in typical working condition.

KW - H.264/AVC

KW - VLSI architecture

KW - Variable block size motion estimation

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UR - http://www.scopus.com/inward/citedby.url?scp=34047130694&partnerID=8YFLogxK

M3 - Conference contribution

AN - SCOPUS:34047130694

SN - 300018726X

SN - 9783000187261

T3 - 25th PCS Proceedings: Picture Coding Symposium 2006, PCS2006

BT - 25th PCS Proceedings

T2 - 25th PCS: Picture Coding Symposium 2006, PCS2006

Y2 - 24 April 2006 through 26 April 2006

ER -

A pipeline parallel tree architecture for full search variable block size motion estimation in H.264/AVC

抄録

出版物シリーズ

Conference

ASJC Scopus subject areas

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