TY - GEN
T1 - A Power-Efficient Soft Error Hardened Latch Design with In-Situ Error Detection Capability
AU - Tajima, Saki
AU - Yanagisawa, Masao
AU - Shi, Youhua
N1 - Publisher Copyright:
© 2019 IEEE.
PY - 2019/11
Y1 - 2019/11
N2 - A power-efficient single node upset hardened latch design with in-situ error detection capability, EDSL, is proposed in this paper for reliability improvement against soft errors. Our simulation results show that the proposed EDSL design can not only recover from any incurred single node upset, but also provide in-situ error detection capability when the latch output is upset. When compared with state-of-the-art error-detection-based and SNU resilient designs, the proposed EDSL latch can achieve up to 72.25% and 79.74% reduction of power-delay-product respectively, which clearly shows the effectiveness of the proposed method.
AB - A power-efficient single node upset hardened latch design with in-situ error detection capability, EDSL, is proposed in this paper for reliability improvement against soft errors. Our simulation results show that the proposed EDSL design can not only recover from any incurred single node upset, but also provide in-situ error detection capability when the latch output is upset. When compared with state-of-the-art error-detection-based and SNU resilient designs, the proposed EDSL latch can achieve up to 72.25% and 79.74% reduction of power-delay-product respectively, which clearly shows the effectiveness of the proposed method.
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U2 - 10.1109/PrimeAsia47521.2019.8950738
DO - 10.1109/PrimeAsia47521.2019.8950738
M3 - Conference contribution
AN - SCOPUS:85078525868
T3 - Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics
SP - 53
EP - 56
BT - Proceedings - PrimeAsia 2019
PB - IEEE Computer Society
T2 - 2019 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, PrimeAsia 2019
Y2 - 11 November 2019 through 14 November 2019
ER -