A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area

Noriyoshi Yamauchi

doi:10.1109/T-ED.1987.23351

A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area

Noriyoshi Yamauchi^*

^*この研究の対応する著者

研究成果: Article › 査読

抄録

A simplified isolation process for test CMOS LSI chip fabrication is proposed. In the process, channel-stop implantation is self-aligned to the p-well and the p-well active area. It is shown that a CMOS device with a one-level metallization can be fabricated with only seven photomasks using the process.

本文言語	English
ページ（範囲）	2562-2563
ページ数	2
ジャーナル	IEEE Transactions on Electron Devices
巻	34
号	12
DOI	https://doi.org/10.1109/T-ED.1987.23351
出版ステータス	Published - 1987
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学
電子材料、光学材料、および磁性材料

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10.1109/T-ED.1987.23351

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A Process for a CMOS Channel-Stop Implantation Self-Aligned to the p-Well and p-Well Active Area

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