A processor core synthesis system in IP-based SoC design

Naoki Tomono; Shunitsu Kohara; Jumpei Uchida; Yuichiro Miyaoka; Nozomu Togawa; Masao Yanagisawa; Tatsuo Ohtsuki

doi:10.1145/1120725.1120851

A processor core synthesis system in IP-based SoC design

Naoki Tomono^*, Shunitsu Kohara, Jumpei Uchida, Yuichiro Miyaoka, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki

^*この研究の対応する著者

基幹理工学部

研究成果: Conference contribution

抄録

This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.

本文言語	English
ホスト出版物のタイトル	Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	286-291
ページ数	6
ISBN（印刷版）	0780387368, 9780780387362
DOI	https://doi.org/10.1145/1120725.1120851
出版ステータス	Published - 2005
イベント	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 - Shanghai, China 継続期間: 2005 1月 18 → 2005 1月 21

出版物シリーズ

名前	Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC
巻	1

Conference

Conference	2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005
国/地域	China
City	Shanghai
Period	05/1/18 → 05/1/21

ASJC Scopus subject areas

コンピュータサイエンスの応用
コンピュータグラフィックスおよびコンピュータ支援設計
電子工学および電気工学

文献へのアクセス

10.1145/1120725.1120851

他のファイルとリンク

引用スタイル

Tomono, N., Kohara, S., Uchida, J., Miyaoka, Y., Togawa, N., Yanagisawa, M., & Ohtsuki, T. (2005). A processor core synthesis system in IP-based SoC design. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005 (pp. 286-291). 記事 1466175 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1145/1120725.1120851

A processor core synthesis system in IP-based SoC design. / Tomono, Naoki; Kohara, Shunitsu; Uchida, Jumpei その他.
Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc., 2005. p. 286-291 1466175 (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC; Vol. 1).

研究成果: Conference contribution

Tomono, N, Kohara, S, Uchida, J, Miyaoka, Y, Togawa, N , Yanagisawa, M & Ohtsuki, T 2005, A processor core synthesis system in IP-based SoC design. in Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005., 1466175, Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC, vol. 1, Institute of Electrical and Electronics Engineers Inc., pp. 286-291, 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005, Shanghai, China, 05/1/18. https://doi.org/10.1145/1120725.1120851

Tomono N, Kohara S, Uchida J, Miyaoka Y, Togawa N , Yanagisawa M その他. A processor core synthesis system in IP-based SoC design. In Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005. Institute of Electrical and Electronics Engineers Inc. 2005. p. 286-291. 1466175. (Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC). doi: 10.1145/1120725.1120851

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AU - Ohtsuki, Tatsuo

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AB - This paper proposes a new design methodology for SoCs reusing hardware IPs. In our approach, after system-level HW/SW partitioning, we use IPs for hardware parts, but synthesize a new processor core instead of reusing a processor core IP. System performs efficient parallel execution of hardware and software by taking account of a response time of hardware IP obtained by the proposed calculation algorithm. We can use optimal hardware IPs selected by the proposed hardware IPs selection algorithm. The experimental results show effectiveness of our new design methodology.

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BT - Proceedings of the 2005 Asia and South Pacific Design Automation Conference, ASP-DAC 2005

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A processor core synthesis system in IP-based SoC design

抄録

出版物シリーズ

Conference

ASJC Scopus subject areas

文献へのアクセス

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