A reconfigurable processor based on ALU array architecture with limitation on the interconnection

Makoto Okada; Tatsuo Hiramatsu; Hiroshi Nakajima; Makoto Ozone; Katsunori Hirase; Shinji Kimura

doi:10.1109/IPDPS.2005.64

A reconfigurable processor based on ALU array architecture with limitation on the interconnection

Makoto Okada^*, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase, Shinji Kimura

^*この研究の対応する著者

大学院情報生産システム研究科

研究成果: Conference contribution

2 被引用数 (Scopus)

抄録

Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is described. To implement reconfigurable system on portable or mobile products, we have tried to develop smaller and powerful reconfigurable processor. We have proposed the ALU array architecture with the limitation on the interconnection for area reduction. By the proposed architecture, we could reduce gate size by 63% on interconnections. Also, we have shown that the performance of proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We have developed compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application.

本文言語	English
ホスト出版物のタイトル	Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
ページ	152a
DOI	https://doi.org/10.1109/IPDPS.2005.64
出版ステータス	Published - 2005 12月 1
イベント	19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 - Denver, CO, United States 継続期間: 2005 4月 4 → 2005 4月 8

出版物シリーズ

名前	Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
巻	2005

Conference

Conference	19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005
国/地域	United States
City	Denver, CO
Period	05/4/4 → 05/4/8

ASJC Scopus subject areas

工学（全般）

文献へのアクセス

10.1109/IPDPS.2005.64

他のファイルとリンク

引用スタイル

Okada, M., Hiramatsu, T., Nakajima, H., Ozone, M., Hirase, K., & Kimura, S. (2005). A reconfigurable processor based on ALU array architecture with limitation on the interconnection. In Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005 (pp. 152a). [1420005] (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005; Vol. 2005). https://doi.org/10.1109/IPDPS.2005.64

A reconfigurable processor based on ALU array architecture with limitation on the interconnection. / Okada, Makoto; Hiramatsu, Tatsuo; Nakajima, Hiroshi その他.
Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 2005. p. 152a 1420005 (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005; Vol. 2005).

研究成果: Conference contribution

Okada, M, Hiramatsu, T, Nakajima, H, Ozone, M, Hirase, K & Kimura, S 2005, A reconfigurable processor based on ALU array architecture with limitation on the interconnection. in Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005., 1420005, Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005, vol. 2005, pp. 152a, 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005, Denver, CO, United States, 05/4/4. https://doi.org/10.1109/IPDPS.2005.64

Okada M, Hiramatsu T, Nakajima H, Ozone M, Hirase K, Kimura S. A reconfigurable processor based on ALU array architecture with limitation on the interconnection. In Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 2005. p. 152a. 1420005. (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005). doi: 10.1109/IPDPS.2005.64

Okada, Makoto ; Hiramatsu, Tatsuo ; Nakajima, Hiroshi その他. / A reconfigurable processor based on ALU array architecture with limitation on the interconnection. Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005. 2005. pp. 152a (Proceedings - 19th IEEE International Parallel and Distributed Processing Symposium, IPDPS 2005).

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abstract = "Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is described. To implement reconfigurable system on portable or mobile products, we have tried to develop smaller and powerful reconfigurable processor. We have proposed the ALU array architecture with the limitation on the interconnection for area reduction. By the proposed architecture, we could reduce gate size by 63% on interconnections. Also, we have shown that the performance of proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We have developed compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application.",

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AB - Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is described. To implement reconfigurable system on portable or mobile products, we have tried to develop smaller and powerful reconfigurable processor. We have proposed the ALU array architecture with the limitation on the interconnection for area reduction. By the proposed architecture, we could reduce gate size by 63% on interconnections. Also, we have shown that the performance of proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We have developed compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application.

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A reconfigurable processor based on ALU array architecture with limitation on the interconnection

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出版物シリーズ

Conference

ASJC Scopus subject areas

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