A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode

Masaki Kumanoya; Kazuyasu Fujishima; Hideshi Miyatake; Nishimura Yasumasa; Kazunori Saito; Takayuki Matsukawa; Tsutomu Yoshihara; Takao Nakano

doi:10.1109/JSSC.1985.1052414

A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode

Masaki Kumanoya, Kazuyasu Fujishima, Hideshi Miyatake, Nishimura Yasumasa, Kazunori Saito, Takayuki Matsukawa, Tsutomu Yoshihara, Takao Nakano

研究成果: Article › 査読

抄録

This paper describes a single 5-V supply 1-Mbit DRAM using a half Vccbiased memory cell with a reduced electric field of 2 MV/cm and a shared sensing scheme for reasonable cell signal. A testability concept which allows 1/4 reduced test time, page/nibble functions including a continuous nibble mode, and an effective redundancy circuit are also described. A typical access time of 90 ns has been obtained using a titanium polycide word-line technology.

本文言語	English
ページ（範囲）	909-913
ページ数	5
ジャーナル	IEEE Journal of Solid-State Circuits
巻	20
号	5
DOI	https://doi.org/10.1109/JSSC.1985.1052414
出版ステータス	Published - 1985
外部発表	はい

ASJC Scopus subject areas

電子工学および電気工学

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10.1109/JSSC.1985.1052414

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AU - Saito, Kazunori

AU - Matsukawa, Takayuki

AU - Yoshihara, Tsutomu

AU - Nakano, Takao

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A Reliable 1-Mbit DRAM with a Multi-Bit-Test Mode

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