A selector-based FFT processor and its FPGA implementation

Yuya Hirai; Kazushi Kawamura; Masao Yanagisawa; Nozomu Togawa

doi:10.1109/ISOCC.2017.8368783

A selector-based FFT processor and its FPGA implementation

Yuya Hirai, Kazushi Kawamura, Masao Yanagisawa, Nozomu Togawa

基幹理工学部

研究成果: Conference contribution

抄録

Fast Fourier transform (FFT) is used in various applications such as signal processings and developing a high-speed FFT processor is quite required. In this paper, we propose a high-speed FFT processor based on selector logics. The selector-based FFT processor is constructed by focusing on the subtract-multiplication operations and partly applying selector logics to them. Furthermore, we implement the selector-based FFT processor on a Xilinx FPGA. Experimental results show that our proposed FFT processor can improve the processing speed by up to 21% and also reduce the number of LUTs by up to 33% compared with a naive FFT processor.

本文言語	English
ホスト出版物のタイトル	Proceedings - International SoC Design Conference 2017, ISOCC 2017
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	88-89
ページ数	2
ISBN（電子版）	9781538622858
DOI	https://doi.org/10.1109/ISOCC.2017.8368783
出版ステータス	Published - 2018 5月 29
イベント	14th International SoC Design Conference, ISOCC 2017 - Seoul, Korea, Republic of 継続期間: 2017 11月 5 → 2017 11月 8

出版物シリーズ

名前	Proceedings - International SoC Design Conference 2017, ISOCC 2017

Other

Other	14th International SoC Design Conference, ISOCC 2017
国/地域	Korea, Republic of
City	Seoul
Period	17/11/5 → 17/11/8

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学
電子材料、光学材料、および磁性材料

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10.1109/ISOCC.2017.8368783

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引用スタイル

Hirai, Y., Kawamura, K., Yanagisawa, M., & Togawa, N. (2018). A selector-based FFT processor and its FPGA implementation. In Proceedings - International SoC Design Conference 2017, ISOCC 2017 (pp. 88-89). (Proceedings - International SoC Design Conference 2017, ISOCC 2017). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC.2017.8368783

Hirai, Y, Kawamura, K, Yanagisawa, M & Togawa, N 2018, A selector-based FFT processor and its FPGA implementation. in Proceedings - International SoC Design Conference 2017, ISOCC 2017. Proceedings - International SoC Design Conference 2017, ISOCC 2017, Institute of Electrical and Electronics Engineers Inc., pp. 88-89, 14th International SoC Design Conference, ISOCC 2017, Seoul, Korea, Republic of, 17/11/5. https://doi.org/10.1109/ISOCC.2017.8368783

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title = "A selector-based FFT processor and its FPGA implementation",

abstract = "Fast Fourier transform (FFT) is used in various applications such as signal processings and developing a high-speed FFT processor is quite required. In this paper, we propose a high-speed FFT processor based on selector logics. The selector-based FFT processor is constructed by focusing on the subtract-multiplication operations and partly applying selector logics to them. Furthermore, we implement the selector-based FFT processor on a Xilinx FPGA. Experimental results show that our proposed FFT processor can improve the processing speed by up to 21% and also reduce the number of LUTs by up to 33% compared with a naive FFT processor.",

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Y1 - 2018/5/29

N2 - Fast Fourier transform (FFT) is used in various applications such as signal processings and developing a high-speed FFT processor is quite required. In this paper, we propose a high-speed FFT processor based on selector logics. The selector-based FFT processor is constructed by focusing on the subtract-multiplication operations and partly applying selector logics to them. Furthermore, we implement the selector-based FFT processor on a Xilinx FPGA. Experimental results show that our proposed FFT processor can improve the processing speed by up to 21% and also reduce the number of LUTs by up to 33% compared with a naive FFT processor.

AB - Fast Fourier transform (FFT) is used in various applications such as signal processings and developing a high-speed FFT processor is quite required. In this paper, we propose a high-speed FFT processor based on selector logics. The selector-based FFT processor is constructed by focusing on the subtract-multiplication operations and partly applying selector logics to them. Furthermore, we implement the selector-based FFT processor on a Xilinx FPGA. Experimental results show that our proposed FFT processor can improve the processing speed by up to 21% and also reduce the number of LUTs by up to 33% compared with a naive FFT processor.

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A selector-based FFT processor and its FPGA implementation

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出版物シリーズ

Other

ASJC Scopus subject areas

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