A sorting-based architecture of finding the first two minimum values for LDPC decoding

Qian Xie; Zhixiang Chen; Xiao Peng; Satoshi Goto

doi:10.1109/CSPA.2011.5759850

A sorting-based architecture of finding the first two minimum values for LDPC decoding

Qian Xie^*, Zhixiang Chen, Xiao Peng, Satoshi Goto

^*この研究の対応する著者

研究成果: Conference contribution

7 被引用数 (Scopus)

抄録

This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.

本文言語	English
ホスト出版物のタイトル	Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011
ページ	95-98
ページ数	4
DOI	https://doi.org/10.1109/CSPA.2011.5759850
出版ステータス	Published - 2011
イベント	2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 - Penang 継続期間: 2011 3月 4 → 2011 3月 6

Other

Other	2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011
City	Penang
Period	11/3/4 → 11/3/6

ASJC Scopus subject areas

信号処理

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10.1109/CSPA.2011.5759850

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引用スタイル

Xie, Q, Chen, Z, Peng, X & Goto, S 2011, A sorting-based architecture of finding the first two minimum values for LDPC decoding. in Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011., 5759850, pp. 95-98, 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011, Penang, 11/3/4. https://doi.org/10.1109/CSPA.2011.5759850

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title = "A sorting-based architecture of finding the first two minimum values for LDPC decoding",

abstract = "This paper presents an efficient architecture of finding the first two minimum values for row operation in LDPC decoding. Given a set of numbers X, efficient algorithm and its corresponding hardware implementation for finding the first minimum value, min-1st, second minimum value, min-2nd and the position of min-1st are greatly needed in LDPC decoder design. The design is based on sorting-based approach proposed in[10]. Compared to the conventional architecture, our architecture performs better in both speed and area. An extension method is also presented to apply the proposed architecture when the number of inputs is an any positive integer.",

keywords = "LDPC codes, LDPC decoder, min-sum algoritm, minimum finder, sorting-based architecture",

author = "Qian Xie and Zhixiang Chen and Xiao Peng and Satoshi Goto",

year = "2011",

doi = "10.1109/CSPA.2011.5759850",

language = "English",

isbn = "9781612844145",

pages = "95--98",

booktitle = "Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011",

note = "2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011 ; Conference date: 04-03-2011 Through 06-03-2011",

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AU - Xie, Qian

AU - Chen, Zhixiang

AU - Peng, Xiao

AU - Goto, Satoshi

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KW - LDPC codes

KW - LDPC decoder

KW - min-sum algoritm

KW - minimum finder

KW - sorting-based architecture

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BT - Proceedings - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011

T2 - 2011 IEEE 7th International Colloquium on Signal Processing and Its Applications, CSPA 2011

Y2 - 4 March 2011 through 6 March 2011

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A sorting-based architecture of finding the first two minimum values for LDPC decoding

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