A sorting-based micro-bump assignment for 3D ICs

Ran Zhang; Tieyuan Pan; Takahiro Watanabe

doi:10.1109/ISOCC.2015.7401697

A sorting-based micro-bump assignment for 3D ICs

Ran Zhang, Tieyuan Pan, Takahiro Watanabe

大学院情報生産システム研究科

研究成果: Conference contribution

3 被引用数 (Scopus)

抄録

Recently RDLs (Re-Distribution Layers) and micro-bumps are widely adopted in 3D IC designs. In this research, a sorting-based micro-bump assignment method is proposed. The approach initially assigns the I/O pads to micro-bumps by sorting the Manhattan distance between them. Then single layer routing in two RDLs are carried out respectively. The experimental results show that the proposed method is able to obtain the routes with shorter total wire length in reasonable CPU times.

本文言語	English
ホスト出版物のタイトル	ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)
出版社	Institute of Electrical and Electronics Engineers Inc.
ページ	139-140
ページ数	2
ISBN（印刷版）	9781467393089
DOI	https://doi.org/10.1109/ISOCC.2015.7401697
出版ステータス	Published - 2016 2月 8
イベント	12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of 継続期間: 2015 11月 2 → 2015 11月 5

Other

Other	12th International SoC Design Conference, ISOCC 2015
国/地域	Korea, Republic of
City	Gyeongju
Period	15/11/2 → 15/11/5

ASJC Scopus subject areas

ハードウェアとアーキテクチャ
電子工学および電気工学
電子材料、光学材料、および磁性材料

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10.1109/ISOCC.2015.7401697

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引用スタイル

Zhang, R, Pan, T & Watanabe, T 2016, A sorting-based micro-bump assignment for 3D ICs. in ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)., 7401697, Institute of Electrical and Electronics Engineers Inc., pp. 139-140, 12th International SoC Design Conference, ISOCC 2015, Gyeongju, Korea, Republic of, 15/11/2. https://doi.org/10.1109/ISOCC.2015.7401697

@inproceedings{4f1fa04fe29a411888ce36a8c22c92ac,

title = "A sorting-based micro-bump assignment for 3D ICs",

abstract = "Recently RDLs (Re-Distribution Layers) and micro-bumps are widely adopted in 3D IC designs. In this research, a sorting-based micro-bump assignment method is proposed. The approach initially assigns the I/O pads to micro-bumps by sorting the Manhattan distance between them. Then single layer routing in two RDLs are carried out respectively. The experimental results show that the proposed method is able to obtain the routes with shorter total wire length in reasonable CPU times.",

keywords = "3D IC, micro-bump assignment, RDL routing",

author = "Ran Zhang and Tieyuan Pan and Takahiro Watanabe",

year = "2016",

month = feb,

day = "8",

doi = "10.1109/ISOCC.2015.7401697",

language = "English",

isbn = "9781467393089",

pages = "139--140",

booktitle = "ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

note = "12th International SoC Design Conference, ISOCC 2015 ; Conference date: 02-11-2015 Through 05-11-2015",

}

TY - GEN

T1 - A sorting-based micro-bump assignment for 3D ICs

AU - Zhang, Ran

AU - Pan, Tieyuan

AU - Watanabe, Takahiro

PY - 2016/2/8

Y1 - 2016/2/8

N2 - Recently RDLs (Re-Distribution Layers) and micro-bumps are widely adopted in 3D IC designs. In this research, a sorting-based micro-bump assignment method is proposed. The approach initially assigns the I/O pads to micro-bumps by sorting the Manhattan distance between them. Then single layer routing in two RDLs are carried out respectively. The experimental results show that the proposed method is able to obtain the routes with shorter total wire length in reasonable CPU times.

AB - Recently RDLs (Re-Distribution Layers) and micro-bumps are widely adopted in 3D IC designs. In this research, a sorting-based micro-bump assignment method is proposed. The approach initially assigns the I/O pads to micro-bumps by sorting the Manhattan distance between them. Then single layer routing in two RDLs are carried out respectively. The experimental results show that the proposed method is able to obtain the routes with shorter total wire length in reasonable CPU times.

KW - 3D IC

KW - micro-bump assignment

KW - RDL routing

UR - http://www.scopus.com/inward/record.url?scp=84963830881&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84963830881&partnerID=8YFLogxK

U2 - 10.1109/ISOCC.2015.7401697

DO - 10.1109/ISOCC.2015.7401697

M3 - Conference contribution

AN - SCOPUS:84963830881

SN - 9781467393089

SP - 139

EP - 140

BT - ISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

PB - Institute of Electrical and Electronics Engineers Inc.

T2 - 12th International SoC Design Conference, ISOCC 2015

Y2 - 2 November 2015 through 5 November 2015

ER -

A sorting-based micro-bump assignment for 3D ICs

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